Resets and Interrupts
Reset and Interrupt Priority
M68HC11E Family — Rev. 5
Data Sheet
MOTOROLA
Resets and Interrupts
97
5.4.1 Highest Priority Interrupt and Miscellaneous Register
RBOOT — Read Bootstrap ROM Bit
Has meaning only when the SMOD bit is a 1 (bootstrap mode or special test
mode). At all other times this bit is clear and cannot be written. Refer to
Section
2. Operating Modes and On-Chip Memory
for more information.
SMOD — Special Mode Select Bit
This bit reflects the inverse of the MODB input pin at the rising edge of reset.
Refer to
Section 2. Operating Modes and On-Chip Memory
for more
information.
MDA — Mode Select A Bit
The mode select A bit reflects the status of the MODA input pin at the rising
edge of reset. Refer to
Section 2. Operating Modes and On-Chip Memory
for
more information.
IRVNE — Internal Read Visibility/Not E Bit
The IRVNE control bit allows internal read accesses to be available on the
external data bus during operation in expanded modes. In single-chip and
bootstrap modes, IRVNE determines whether the E clock is driven out an
external pin. For the MC68HC811E2, this bit is IRV and only controls internal
read visibility. Refer to
Section 2. Operating Modes and On-Chip Memory
for
more information.
PSEL[3:0] — Priority Select Bits
These bits select one interrupt source to be elevated above all other I-bit-related
sources and can be written only while the I bit in the CCR is set (interrupts
disabled).
Address:
$103C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
RBOOT
(1)
SMOD
(1)
MDA
(1)
IRVNE
PSEL2
PSEL2
PSEL1
PSEL0
Write:
Reset:
Single chip:
0
0
0
0
0
1
1
0
Expanded:
0
0
1
0
0
1
1
0
Bootstrap:
1
1
0
0
0
1
1
0
Special test:
1. The values of the RBOOT, SMOD, and MDA reset bits depend on the mode selected at the
RESET pin rising edge. Refer to
Table 2-1. Hardware Mode Select Summary
.
0
1
1
1
0
1
1
0
Figure 5-4. Highest Priority I-Bit Interrupt
and Miscellaneous Register (HPRIO)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.