Operating Modes and On-Chip Memory
Memory Map
M68HC11E Family — Rev. 5
Data Sheet
MOTOROLA
Operating Modes and On-Chip Memory
For More Information On This Product,
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39
$1005
Port C Latched Register
(PORTCL)
See page 112.
Read:
Write:
Reset:
PCL7
PCL6
PCL5
PCL4
PCL3
PCL2
PCL1
PCL0
Indeterminate after reset
R
$1006
Reserved
R
R
R
R
R
R
R
$1007
Port C Data Direction Register
(DDRC)
See page 112.
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
0
$1008
Port D Data Register
(PORTD)
See page 112.
0
0
PD5
PD4
PD3
PD2
PD1
PD0
U
U
I
I
I
I
I
I
$1009
Port D Data Direction Register
(DDRD)
See page 113.
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
0
0
0
0
0
0
0
0
$100A
Port E Data Register
(PORTE)
See page 113.
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
Indeterminate after reset
$100B
Timer Compare Force Register
(CFORC)
See page 151.
FOC1
FOC2
FOC3
FOC4
FOC5
0
0
0
0
0
0
0
0
$100C
Output Compare 1 Mask Register
(OC1M)
See page 152.
OC1M7
OC1M6
OC1M5
OC1M4
OC1M3
0
0
0
0
0
0
0
0
$100D
Output Compare 1 Data Register
(OC1D)
See page 152.
OC1D7
OC1D6
OC1D5
OC1D4
OC1D3
0
0
0
0
0
0
0
0
$100E
Timer Counter Register High
(TCNTH)
See page 153.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
$100F
Timer Counter Register Low
(TCNTL)
See page 153.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
$1010
Timer Input Capture 1 Register
High (TIC1H)
See page 147.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Indeterminate after reset
$1011
Timer Input Capture 1 Register
Low (TIC1L)
See page 147.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Indeterminate after reset
R
= Reserved
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented
U = Unaffected
I = Indeterminate after reset
Figure 2-7. Register and Control Bit Assignments (Sheet 2 of 6)
F
Freescale Semiconductor, Inc.
n
.