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參數(shù)資料
| 型號(hào)： | MC68HC11E9BCFU2 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | POT 20K OHM 1/2 SQ CERM SL MT |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁(yè)數(shù)： | 173/268頁(yè) |
| 文件大?。?/td> | 3696K |
| 代理商： | MC68HC11E9BCFU2 |
Electrical Characteristics
MC68L11E9/E20 Control Timing
M68HC11E Family — Rev. 5
Data Sheet
MOTOROLA
Electrical Characteristics
173
10.10 MC68L11E9/E20 Control Timing
Figure 10-2. Timer Inputs
Characteristic
(1)
(2)
Symbol
1.0 MHz
2.0 MHz
Unit
Min
Max
Min
Max
Frequency of operation
f
o
dc
1.0
dc
2.0
MHz
E-clock period
t
CYC
1000
—
500
—
ns
Crystal frequency
f
XTAL
—
4.0
—
8.0
MHz
External oscillator frequency
4 f
o
dc
4.0
dc
8.0
MHz
Processor control setup time
t
PCSU
= 1/4 t
CYC
+ 75 ns
t
PCSU
325
—
200
—
ns
Reset input pulse width
To guarantee external reset vector
Minimum input time (can be pre-empted by internal reset)
PW
RSTL
8
1
—
—
8
1
—
—
t
CYC
Mode programming setup time
t
MPS
2
—
2
—
t
CYC
Mode programming hold time
t
MPH
10
—
10
—
ns
Interrupt pulse width, IRQ edge-sensitive mode
PW
IRQ
= t
CYC
+ 20 ns
PW
IRQ
1020
—
520
—
ns
Wait recovery startup time
t
WRS
—
4
—
4
t
CYC
Timer pulse width input capture pulse accumulator input
PW
TIM
= t
CYC
+ 20 ns
PW
TIM
1020
—
520
—
ns
1. V
DD
= 3.0 Vdc to 5.5 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, all timing is shown with respect to 20% V
DD
and 70% V
DD
, unless
otherwise noted
2. RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles,
releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to
Section 5.
Resets and Interrupts
for further detail.
Notes
:
1. Rising edge sensitive input
2. Falling edge sensitive input
3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2.
PA7
(2) (3)
PA7
(1) (3)
PA[2:0]
(2)
PA[2:0]
(1)
PW
TIM
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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