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參數(shù)資料
| 型號： | MC68HC11D3CFN3 |
| 廠商： | ABILIS SYSTEMS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 132/138頁 |
| 文件大?。?/td> | 1047K |
| 代理商： | MC68HC11D3CFN3 |
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Output Compare (OC)
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
93
8.4.2 Timer Compare Force Register
The timer compare force register (CFORC) allows forced early compares. FOC1–FOC5 correspond to
the five output compares. These bits are set for each output compare that is to be forced. The action taken
as a result of a forced compare is the same as if there were a match between the OCx register and the
free-running counter, except that the corresponding interrupt status flag bits are not set. The forced
channels trigger their programmed pin actions to occur at the next timer count transition after the write to
CFORC.
The CFORC bits should not be used on an output compare function that is programmed to toggle its
output on a successful compare because a normal compare that occurs immediately before or after the
force can result in an undesirable operation.
FOC1–FOC5 — Write 1s to Force Compare Bits
0 = Not affected
1 = Output x action occurs
Bits 2–0 — Not implemented, always read 0.
8.4.3 Output Compare 1 Mask Register
Use OC1M with OC1 to specify the bits of port A that are affected by a successful OC1 compare. The bits
of the OC1M register correspond to PA7–PA3.
OC1M7–OC1M3 — Output Compare Masks
0 = OC1 disabled
1 = OC1 enabled to control the corresponding pin of port A
Bits 2–0 — Not implemented; always read 0.
Set bit(s) to enable OC1 to control corresponding pin(s) of port A.
Address:
$000B
Bit 7
654321
Bit 0
Read:
FOC1
FOC2
FOC3
FOC4
FOC5
0
Write:
Reset:
00000000
Figure 8-7. Timer Compare Force Register (CFORC)
Address:
$000C
Bit 7
654321
Bit 0
Read:
OC1M7
OC1M6
OC1M5
OC1M4
OC1M3
0
Write:
Reset:
00000000
Figure 8-8. Output Compare 1 Mask Register (OC1M)
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