參數(shù)資料
型號: MC68HC11D3CFN2
廠商: ABILIS SYSTEMS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 12/138頁
文件大?。?/td> 1047K
代理商: MC68HC11D3CFN2
Control Timing
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
109
9.6 Control Timing
Figure 9-3. Timer Inputs
Characteristic(1)
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted.
Symbol
1.0 MHz
2.0 MHz
3.0 MHz
Unit
Min
Max
Min
Max
Min
Max
Frequency of operation
fO
dc
1.0
dc
2.0
dc
3.0
MHz
E-clock period
tcyc
1000
500
333
ns
Crystal frequency
fXTAL
—4.0
8.0
12.0
MHz
External oscillator frequency
4 fO
dc
4.0
dc
8.0
dc
12.0
MHz
Processor control setup timetPCSU = 1/4 tcyc + 50 ns
tPCSU
300
175
133
ns
Reset input pulse width(2)
To guarantee external reset vector
Minimum input time can be preempted by internal reset
2. Reset is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles,
releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to Chapter 5
Input/Output (I/O) Ports for further details.
PWRSTL
8
1
8
1
8
1
tcyc
Mode programming setup time
tMPS
2—
2
2
tcyc
Mode programming hold time
tMPH
10
10
10
ns
Interrupt pulse width, PWIRQ = tcyc + 20 ns
IRQ edge-sensitive mode
PWIRQ
1020
520
353
ns
Wait recovery startup time
tWRS
4
—4—4
tcyc
Timer pulse width PWTIM = tcyc + 20 ns
Input capture pulse
Accumulator input
PWTIM
1020
520
353
ns
Notes:
1. Rising edge sensitive input
2. Falling edge sensitive input
3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2.
PA7(2) (3)
PA7(1) (3)
PA0–PA3(2)
PA0–PA3(1)
PWTIM
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