
MOTOROLA
ELECTRICAL CHARACTERISTICS
MC68HC11D3
A-12
TECHNICAL DATA
Figure A-9 SPI Master Timing (CPHA = 0)
Figure A-10 SPI Master Timing (CPHA = 1)
SPI MASTER CPHA0 TIM
SEE
NOTE
NOTE: This first clock edge is generated internally but is not seen at the SCK pin.
SCK (CPOL = 0)
(OUTPUT)
SCK (CPOL = 1)
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
SS
(INPUT)
1
SEE
NOTE
11
6
7
MSB IN
BIT 6 - - - -1
LSB IN
MASTER MSB OUT
MASTER LSB OUT
BIT 6 - - - -1
10
12
13
SS is held high on master.
5
4
13
12
11 (ref)
10 (ref)
13
4
5
12
SPI MASTER CPHA1 TIM
NOTE: This last clock edge is generated internally but is not seen at the SCK pin.
4
5
4
1
SEE
NOTE
11
6
7
MSB IN
LSB IN
MASTER MSB OUT
MASTER LSB OUT
BIT 6 - - - -1
10
13
12
13
12
SCK (CPOL = 0)
(OUTPUT)
SCK (CPOL = 1)
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
SS
(INPUT)
SS is held high on master.
SEE
NOTE
12
13
BIT 6 - - - -1
11 (ref)
10 (ref)