參數(shù)資料
型號: MC68HC11A8BCP2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: HCMOS Single-Chip Microcontroller
中文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48
封裝: DIP-48
文件頁數(shù): 117/158頁
文件大小: 776K
代理商: MC68HC11A8BCP2
MC68HC11A8
TECHNICAL DATA
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MOTOROLA
10-19
10
5-11
CPD, CPY
7
1
2
3
4
5
6
7
1
2
3
4
5
6
Opcode Address
Opcode Address + 1
Opcode Address + 2
Opcode Address + 3
Operand Address
Operand Address + 1
$FFFF
Opcode Address
Opcode Address + 1
Opcode Address + 2
Subroutine Address
Stack Pointer
Stack Pointer – 1
1
1
1
1
1
1
1
1
1
1
1
0
0
Opcode (Page Select Byte)
Opcode (Second Byte)
Operand Address (High Byte)
Operand Address (Low Byte)
Operand Data (High Byte)
Operand Data (Low Byte)
Irrelevant Data
Opcode ($BD)
Subroutine Address (High Byte)
Subroutine Address (Low Byte)
First Opcode in Subroutine
Return Address (Low Byte)
Return Address (High Byte)
5-12
JSR
6
Table 10-6 Cycle-by-Cycle Operation — Indexed X Mode (Sheet 1 of 2)
Reference
Number*
6-1
Address Mode
and Instructions
JMP
Cycles Cycle
#
1
2
3
1
2
3
4
Address Bus
R/W
Line
1
1
1
1
1
1
1
Data Bus
3
Opcode Address
Opcode Address + 1
$FFFF
Opcode Address
Opcode Address + 1
$FFFF
(IX) + Offset
Opcode ($6E)
Index Offset
Irrelevant Data
Opcode
Index Offset
Irrelevant Data
Operand Data
6-2
ADCA, ADCB, ADDA,
ADDB, ANDA, ANDB,
BITA, BITB, CMPA,
CMPB, EORA, EORB,
LDAA, LDAB, ORAA,
ORAB, SBCA, SBCB,
SUBA, SUBB
ASL, ASR, CLR,
COM, DEC, INC,
LSL, LSR, NEG,
ROL, ROR
4
6-3
6
1
2
3
4
5
6
1
2
3
4
5
6
1
2
3
4
1
2
3
4
5
Opcode Address
Opcode Address + 1
$FFFF
(IX) + Offset
$FFFF
(IX) + Offset
Opcode Address
Opcode Address + 1
$FFFF
(IX) + Offset
$FFFF
$FFFF
Opcode Address
Opcode Address + 1
$FFFF
(IX) + Offset
Opcode Address
Opcode Address + 1
$FFFF
(IX) + Offset
(IX) + Offset + 1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
Opcode
Index Offset
Irrelevant Data
Original Operand Data
Irrelevant Data
Result Operand Data
Opcode ($6D)
Index Offset
Irrelevant Data
Original Operand Data
Irrelevant Data
Irrelevant Data
Opcode
Index Offset
Irrelevant Data
Accumulator Data
Opcode
Index Offset
Irrelevant Data
Operand Data (High Byte)
Operand Data (Low Byte)
6-4
TST
6
6-5
STAA, STAB
4
6-6
LDD, LDS, LDX
5
*The reference number is given to provide a cross-reference to Table 10-1.
Table 10-5 Cycle-by-Cycle Operation — Extended Mode (Sheet 2 of 2)
Reference
Number*
Address Mode
and Instructions
Cycles Cycle
#
Address Bus
R/W
Line
Data Bus
*The reference number is given to provide a cross-reference to Table 10-1.
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