參數(shù)資料
型號(hào)： MC68HC11A8BCFN2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52
封裝： PLASTIC, LCC-52
文件頁數(shù)： 7/158頁
文件大?。?/td> 3803K
代理商： MC68HC11A8BCFN2
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MC68HC11A8
10-6
TECHNICAL DATA
10
Table 10-1 MC68HC11A8 Instructions, Addressing Modes, and Execution Times
(Sheet 1 of 6)
Source
Form(s)
Operation
Boolean Expression
Addressing
Mode for
Operand
Machine Coding
(Hexadecimal)
Bytes
Cycle
by
Cycle*
Condition Codes
Opcode
Operand(s)
S X H I N Z V C
ABA
Add Accumulators
A + B
→ A
INH
1B
1
2
2-1
- - ¤ - ¤ ¤ ¤ ¤
ABX
Add B to X
IX + 00:B
→ IX
INH
3A
1
3
2-2
- - - - - - - -
ABY
Add B to Y
IY + 00:B
→ IY
INH
18 3A
2
4
2-4
- - - - - - - -
ADCA
(opr)
Add with Carry to A
A + M + C
→ A
A IMM
A DIR
A EXT
A IND,X
A IND,Y
89
99
B9
A9
18 A9
ii
dd
hh
ll
ff
2
3
2
3
2
3
4
5
3-1
4-1
5-2
6-2
7-2
- - ¤ - ¤ ¤ ¤ ¤
ADCB (opr) Add with Carry to B
B + M + C
→ B
B IMM
B DIR
B EXT
B IND,X
B IND,Y
C9
D9
F9
E9
18 E9
ii
dd
hh
ll
ff
2
3
2
3
2
3
4
5
3-1
4-1
5-2
6-2
7-2
- - ¤ - ¤ ¤ ¤ ¤
ADDA (opr) Add Memory to A
A + M
→ A
A IMM
A DIR
A EXT
A IND,X
A IND,Y
8B
9B
BB
AB
18 AB
ii
dd
hh
ll
ff
2
3
2
3
2
3
4
5
3-1
4-1
5-2
6-2
7-2
- - ¤ - ¤ ¤ ¤ ¤
ADDB (opr) Add Memory to B
B + M
→ B
B IMM
B DIR
B EXT
B IND,X
B IND,Y
CB
DB
FB
EB
18 EB
ii
dd
hh
ll
ff
2
3
2
3
2
3
4
5
3-1
4-1
5-2
6-2
7-2
- - ¤ - ¤ ¤ ¤ ¤
ADDD (opr) Add 16-Bit to D
D + M:M + 1
→ D
IMM
DIR
EXT
IND,X
IND,Y
C3
D3
F3
E3
18 E3
jj
kk
dd
hh
ll
ff
3
2
3
2
3
4
5
6
7
3-3
4-7
5-10
6-10
7-8
- - - - ¤ ¤ ¤ ¤
ANDA (opr) AND A with Memory
AM
→ A
A IMM
A DIR
A EXT
A IND,X
A IND,Y
84
94
B4
A4
18 A4
ii
dd
hh
ll
ff
2
3
2
3
2
3
4
5
3-1
4-1
5-2
6-2
7-2
- - - - ¤ ¤ 0 -
ANDB (opr) AND B with Memory
BM
→ B
B IMM
B DIR
B EXT
B IND,X
B IND,Y
C4
D4
F4
E4
18 E4
ii
dd
hh
ll
ff
2
3
2
3
2
3
4
5
3-1
4-1
5-2
6-2
7-2
- - - - ¤ ¤ 0 -
ASL (opr)
Arithmetic Shift Left
EXT
IND,X
IND,Y
A INH
B INH
78
68
18 68
48
58
hh
ll
ff
3
2
3
1
6
7
2
5-8
6-3
7-3
2-1
- - - - ¤ ¤ ¤ ¤
ASLA
ASLB
ASLD
Arithmetic Shift Left Double
INH
05
1
3
2-2
- - - - ¤ ¤ ¤ ¤
ASR (opr)
Arithmetic Shift Right
EXT
IND,X
IND,Y
A INH
B INH
77
67
18 67
47
57
hh
ll
ff
3
2
3
1
6
7
2
5-8
6-3
7-3
2-1
- - - - ¤ ¤ ¤ ¤
ASRA
ASRB
BCC (rel)
Branch if Carry Clear
? C = 0
REL
24 rr
2
3
8-1
- - - - - - - -
BCLR (opr)
(msk)
Clear Bit(s)
M(mm)
→ M
DIR
IND,X
IND,Y
15
1D
18 1D
dd
mm
ff
mm
ff
mm
3
4
6
7
8
4-10
6-13
7-10
- - - - ¤ ¤ 0 -
BCS (rel)
Branch if Carry Set
? C = 1
REL
25 rr
2
3
8-1
- - - - - - - -
BEQ (rel)
Branch if = Zero
? Z = 1
REL
27 rr
2
3
8-1
- - - - - - - -
BGE (rel)
Branch if
≥ Zero
? N
⊕ V = 0
REL
2C rr
2
3
8-1
- - - - - - - -
BGT (rel)
Branch if > Zero
? Z + (N
⊕ V) = 0
REL
2E rr
2
3
8-1
- - - - - - - -
BHI (rel)
Branch if Higher
? C + Z = 0
REL
22 rr
2
3
8-1
- - - - - - - -
BHS (rel)
Branch if Higher or Same
? C = 0
REL
24 rr
2
3
8-1
- - - - - - - -
*Cycle-by-cycle number provides a reference to Tables 10-2 through 10-8 which detail cycle-by-cycle operation.
Example: Table 10-1 Cycle-by-Cycle column reference number 2-4 equals Table 10-2 line item 2-4.
Cb0
b7
0
Cb0
b15
0
C
b0
b7
F
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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