參數(shù)資料
型號： MC68HC11A0CP2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48
封裝： PLASTIC, DIP-48
文件頁數(shù)： 9/158頁
文件大小： 3803K
代理商： MC68HC11A0CP2
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MC68HC11A8
10-8
TECHNICAL DATA
10
CPX (opr)
Compare X to Memory 16-Bit
IX – M:M + 1
IMM
DIR
EXT
IND,X
IND,Y
8C
9C
BC
AC
CD AC
jj
kk
dd
hh
ll
ff
3
2
3
2
3
4
5
6
7
3-3
4-7
5-10
6-10
7-8
- - - - ¤ ¤ ¤ ¤
CPY (opr)
Compare Y to Memory
16-Bit
IY – M:M + 1
IMM
DIR
EXT
IND,X
IND,Y
18 8C
18 9C
18 BC
1A AC
18 AC
jj
kk
dd
hh
ll
ff
4
3
4
3
5
6
7
3-5
4-9
5-11
6-11
7-8
- - - - ¤ ¤ ¤ ¤
DAA
Decimal Adjust A
Adjust Sum to BCD
INH
19
1
2
2-1
- - - - ¤ ¤ ¤ ¤
DEC (opr)
Decrement Memory Byte
M – 1
→ M
EXT
IND,X
IND,Y
7A
6A
18 6A
hh
ll
ff
3
2
3
6
7
5-8
6-3
7-3
- - - - ¤ ¤ ¤ -
DECA
Decrement Accumulator A
A – 1
→ A
A INH
4A
1
2
2-1
- - - - ¤ ¤ ¤ -
DECB
Decrement Accumulator B
B – 1
→ B
B INH
5A
1
2
2-1
- - - - ¤ ¤ ¤ -
DES
Decrement Stack Pointer
SP – 1
→ SP
INH
34
1
3
2-3
- - - - - - - -
DEX
Decrement Index Register X
IX – 1
→ IX
INH
09
1
3
2-2
- - - - - ¤ - -
DEY
Decrement Index Register Y
IY – 1
→ IY
INH
18 09
2
4
2-4
- - - - - ¤ - -
EORA (opr) Exclusive OR A with Memory
A
⊕ M → A
A IMM
A DIR
A EXT
A IND,X
A IND,Y
88
98
88
A8
18 A8
ii
dd
hh
ll
ff
2
3
2
3
2
3
4
5
3-1
4-1
5-2
6-2
7-2
- - - - ¤ ¤ 0 -
EORB (opr) Exclusive OR B with Memory
B
⊕ M → B
B IMM
B DIR
B EXT
B IND,X
B IND,Y
C8
D8
F8
E8
18 E8
ii
dd
hh
ll
ff
2
3
2
3
2
3
4
5
3-1
4-1
5-2
6-2
7-2
- - - - ¤ ¤ 0 -
FDIV
Fractional Divide 16 by 16
D/IX
→ IX; r → D
INH
03
1
41
2-17
- - - - - ¤ ¤ ¤
IDIV
Integer Divide 16 by 16
D/IX
→ IX; r → D
INH
02
1
41
2-17
- - - - - ¤ 0 ¤
INC (opr)
Increment Memory Byte
M + 1
→ M
EXT
IND,X
IND,Y
7C
6C
18 6C
hh
ll
ff
3
2
3
6
7
5-8
6-3
7-3
- - - - ¤ ¤ ¤ -
INCA
Increment Accumulator A
A + 1
→ A
A INH
4C
1
2
2-1
- - - - ¤ ¤ ¤ -
INCB
Increment Accumulator B
B + 1
→ B
B INH
5C
1
2
2-1
- - - - ¤ ¤ ¤ -
INS
Increment Stack Pointer
SP + 1
→ SP
INH
31
1
3
2-3
- - - - - - - -
INX
Increment Index Register X
IX + 1
→ IX
INH
08
1
3
2-2
- - - - - ¤ - -
INY
Increment Index Register Y
IY + 1
→ IY
INH
18 08
2
4
2-4
- - - - - ¤ - -
JMP (opr)
Jump
See Special Ops
EXT
IND,X
IND,Y
7E
6E
18 6E
hh
ll
ff
3
2
3
4
5-1
6-1
7-1
- - - - - - - -
JSR (opr)
Jump to Subroutine
See Special Ops
DIR
EXT
IND,X
IND,Y
9D
BD
AD
18 AD
dd
hh
ll
ff
2
3
2
3
5
6
7
4-8
5-12
6-12
7-9
- - - - - - - -
LDAA (opr) Load Accumulator A
M
→ A
A IMM
A DIR
A EXT
A IND,X
A IND,Y
86
96
B6
A6
18 A6
ii
dd
hh
ll
ff
2
3
2
3
2
3
4
5
3-1
4-1
5-2
6-2
7-2
- - - - ¤ ¤ 0 -
LDAB (opr) Load Accumulator B
M
→ B
B IMM
B DIR
B EXT
B IND,X
B IND,Y
C6
D6
F6
E6
18 E6
ii
dd
hh
ll
ff
2
3
2
3
2
3
4
5
3-1
4-1
5-2
6-2
7-2
- - - - ¤ ¤ 0 -
LDD (opr)
Load Double Accumulator D
M
→ A,M + 1 → B
IMM
DIR
EXT
IND,X
IND,Y
CC
DC
FC
EC
18 EC
jj
kk
dd
hh
ll
ff
3
2
3
2
3
4
5
6
3-2
4-3
5-4
6-6
7-6
- - - - ¤ ¤ 0 -
Table 10-1 MC68HC11A8 Instructions, Addressing Modes, and Execution Times
(Sheet 3 of 6)
Source
Form(s)
Operation
Boolean Expression
Addressing
Mode for
Operand
Machine Coding
(Hexadecimal)
Bytes
Cycle
by
Cycle*
Condition Codes
Opcode
Operand(s)
S X H I N Z V C
*Cycle-by-cycle number provides a reference to Tables 10-2 through 10-8 which detail cycle-by-cycle operation.
Example: Table 10-1 Cycle-by-Cycle column reference number 2-4 equals Table 10-2 line item 2-4.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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