參數(shù)資料
型號: MC68HC11A0CFN2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: HCMOS Single-Chip Microcontroller
中文描述: 8-BIT, 2 MHz, MICROCONTROLLER, PQCC52
封裝: PLASTIC, LCC-52
文件頁數(shù): 5/158頁
文件大小: 776K
代理商: MC68HC11A0CFN2
MC68HC11A8
TECHNICAL DATA
MOTOROLA
v
6.2.4
6.3
6.4
6.4.1
6.4.2
6.4.3
Slave Select (SS) ..............................................................................6-2
Functional Description ...............................................................................6-3
SPI Registers ............................................................................................6-4
Serial Peripheral Control Register (SPCR) .......................................6-4
Serial Peripheral Status Register (SPSR) .........................................6-5
Serial Peripheral Data l/O Register (SPDR) ......................................6-6
7 ANALOG-TO-DIGITAL CONVERTER
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Conversion Process ..................................................................................7-1
Channel Assignments ...............................................................................7-1
Single-Channel Operation .........................................................................7-2
Multiple-Channel Operation .......................................................................7-2
Operation in STOP and WAIT Modes .......................................................7-3
A/D Control/Status Register (ADCTL) .......................................................7-3
A/D Result Registers 1, 2, 3, and 4 (ADR1, ADR2, ADR3, and ADR4) ....7-5
A/D Power-Up and Clock Select ...............................................................7-5
8 PROGRAMMABLE TIMER, RTI, AND PULSE ACCUMULATOR
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.1.8
8.1.9
8.1.10
8.1.11
8.1.12
8.1.13
8.2
8.3
8.3.1
Programmable Timer .................................................................................8-1
Counter ..............................................................................................8-1
Input Capture .....................................................................................8-1
Output Compare ................................................................................8-2
Output Compare 1 I/O Pin Control ....................................................8-2
Timer Compare Force Register (CFORC) .........................................8-3
Output Compare 1 Mask Register (OC1M) .......................................8-3
Output Compare 1 Data Register (OC1D) ........................................8-4
Timer Control Register 1 (TCTL1) .....................................................8-4
Timer Control Register 2 (TCTL2) .....................................................8-5
Timer Interrupt Mask Register 1 (TMSK1) ........................................8-5
Timer Interrupt Flag Register 1 (TFLG1) ...........................................8-5
Timer Interrupt Mask Register 2 (TMSK2) ........................................8-6
Timer Interrupt Flag Register 2 (TFLG2) ...........................................8-7
Real-Time Interrupt ...................................................................................8-8
Pulse Accumulator ....................................................................................8-8
Pulse Accumulator Control Register (PACTL) ..................................8-8
9 RESETS, INTERRUPTS, AND LOW POWER MODES
9.1
9.1.1
9.1.2
9.1.2.1
9.1.2.2
9.1.2.3
9.1.2.4
9.1.2.5
Resets .......................................................................................................9-1
External RESET Pin ..........................................................................9-1
Power-On Reset ................................................................................9-1
CPU ...........................................................................................9-2
Memory Map .............................................................................9-3
Parallel l/O .................................................................................9-3
Timer .........................................................................................9-3
Real-Time Interrupt ...................................................................9-4
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