
Timer Interface Module (TIM)
Functional Description
MC68HC(9)08XK48 — Rev. 4.0
Advance Information
MOTOROLA
Timer Interface Module (TIM)
257
Channels 2 and 3 can be linked to form a buffered PWM channel whose
output appears on the PTE6/TCH2 pin. The timer channel registers of
the linked pair alternately control the pulse width of the output.
Setting the MS2B bit in timer channel 2 status and control register
(TSC2) links channel 2 and channel 3. The timer channel 2 registers
initially control the pulse width on the PTE6/TCH2 pin. Writing to the
timer channel 3 registers enables the timer channel 3 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the timer channel registers (2 or 3)
that control the pulse width are the ones written to last. TSC2 controls
and monitors the buffered PWM function, and timer channel 3 status and
control register (TSC3) is unused.
NOTE:
In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. Writing to the active channel
registers is the same as generating unbuffered PWM signals.
16.4.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered
PWM signals, use this initialization procedure:
1. In the timer status and control register (TSC):
a.
Stop the timer counter by setting the timer stop bit, TSTOP.
b.
Reset the timer counter by setting the timer reset bit, TRST.
2. In the timer counter modulo registers (TMODH:TMODL), write the
value for the required PWM period.
3. In the timer channel x registers (TCHxH:TCHxL), write the value
for the required pulse width.
4. In timer channel x status and control register (TSCx):
a.
Write 0:1 (for unbuffered output compare or PWM signals) or
1:0 (for buffered output compare or PWM signals) to the mode
b.
Write 1 to the toggle-on-overflow bit, TOVx.