參數(shù)資料
型號(hào)： MC68HC08QT2MDWE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO8
封裝： LEAD FREE, EIAJ, SOIC-8
文件頁數(shù)： 41/176頁
文件大?。?/td> 1124K
代理商： MC68HC08QT2MDWE
Break Module (BRK)
MC68HC08QY/QT Family Data Sheet, Rev. 2
Freescale Semiconductor
135
The break interrupt timing is:
When a break address is placed at the address of the instruction opcode, the instruction is not
executed until after completion of the break interrupt routine.
When a break address is placed at an address of an instruction operand, the instruction is executed
before the break interrupt.
When software writes a 1 to the BRKA bit, the break interrupt occurs just before the next instruction
is executed.
By updating a break address and clearing the BRKA bit in a break interrupt routine, a break interrupt can
be generated continuously.
CAUTION
A break address should be placed at the address of the instruction opcode.
When software does not change the break address and clears the BRKA
bit in the first break interrupt routine, the next break interrupt will not be
generated after exiting the interrupt routine even when the internal address
bus matches the value written in the break address registers.
15.2.1.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See 13.8.2 Break Flag Control Register and the Break Interrupts subsection
for each module.
15.2.1.2 TIM During Break Interrupts
A break interrupt stops the timer counter.
15.2.1.3 COP During Break Interrupts
The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary
register (BRKAR).
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