
NON-DISCLOSURE
AGREEMENT
REQUIRED
Clock Generator Module (CGM)
Technical Data
MC68HC08QA24
108
Clock Generator Module (CGM)
MOTOROLA
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. For maximum immunity guidelines, refer to:
Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers, Motorola document order number AN1050/D
Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers, Motorola document order number AN1263
These application notes on electromagnetic compatibility are available
from local Motorola sales offices.) The VCO frequency is bound to a
range from roughly one-half to twice the center-of-range frequency,
fVRS. Modulating the voltage on the CGMXFC pin changes the
frequency within this range. By design, fVRS is equal to the nominal
center-of-range frequency, fNOM, 4.9152 MHz times a linear factor (L) or
fNOM.
CGMXCLK is the PLL reference clock which runs at the crystal
frequency, fXCLK,
The VCO’s output clock, CGMVCLK, running at a frequency fVCLK is fed
back through a programmable modulo divider. The modulo divider
PLL). The divider’s output is the VCO feedback clock, CGMVDV,
The phase detector then compares the VCO feedback clock (CGMVDV)
with the reference clock (CGMXCLK). A correction pulse is generated
based on the phase difference between the two signals. The loop filter
then slightly alters the dc voltage on the external capacitor connected to
CGMXFC, based on the width and direction of the correction pulse. The
filter can make fast or slow corrections, depending on its mode,
external capacitor and the reference frequency determines the speed of
the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the reference clock, CGMXCLK. Therefore, the speed of
the lock detector is directly proportional to the reference frequency,
fXCLK. The circuit determines the mode of the PLL and the lock condition
based on this comparison.