
Timer Interface Module (TIM)
MC68HC908JL8/JK8 MC68HC08JL8/JK8 MC68HC908KL8 Data Sheet, Rev. 3.1
108
Freescale Semiconductor
8.4.1 TIM Counter Prescaler
The TIM1 clock source can be one of the seven prescaler outputs; TIM2 clock source can be one of the
seven prescaler outputs or the TIM2 clock pin, T2CLK. The prescaler generates seven clock rates from
the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register select the
TIM clock source.
8.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter
into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input
captures can generate TIM CPU interrupt requests.
8.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU
interrupt requests.
$0034
TIM2 Counter Modulo
Register Low
(T2MODL)
Read:
Bit 7
654321
Bit 0
Write:
Reset:
11111111
$0035
TIM2 Channel 0 Status
and Control Register
(T2SC0)
Read:
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
Write:
0
Reset:
00000000
$0036
TIM2 Channel 0
Register High
(T2CH0H)
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
Indeterminate after reset
$0037
TIM2 Channel 0
Register Low
(T2CH0L)
Read:
Bit 7
654321
Bit 0
Write:
Reset:
Indeterminate after reset
$0038
TIM2 Channel 1 Status
and Control Register
(T2SC1)
Read:
CH1F
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
Write:
0
Reset:
00000000
$0039
TIM2 Channel 1
Register High
(T2CH1H)
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
Indeterminate after reset
$003A
TIM2 Channel 1
Register Low
(T2CH1L)
Read:
Bit 7
654321
Bit 0
Write:
Reset:
Indeterminate after reset
Addr.
Register Name
Bit 7
654321
Bit 0
= Unimplemented
Figure 8-2. TIM I/O Register Summary (Sheet 2 of 2)