Central Processor Unit (CPU)
MC68HC908JL3E Family Data Sheet, Rev. 4
42
Freescale Semiconductor
4.7 Instruction Set Summary
Table 4-1
provides a summary of the M68HC08 instruction set.
Table 4-1. Instruction Set Summary (Sheet 1 of 6)
Source
Form
Operation
Description
Effect
on CCR
A
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
M
O
A9
B9
C9
D9
E9
F9
9EE9
9ED9
AB
BB
CB
DB
EB
FB
9EEB
9EDB
A7
O
C
2
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
2
V H I N Z C
ADC #
opr
ADC
opr
ADC
opr
ADC
opr
,X
ADC
opr
,X
ADC ,X
ADC
opr
,SP
ADC
opr
,SP
ADD #
opr
ADD
opr
ADD
opr
ADD
opr
,X
ADD
opr
,X
ADD ,X
ADD
opr
,SP
ADD
opr
,SP
AIS #
opr
Add with Carry
A
←
(A) + (M) + (C)
–
ii
dd
hh ll
ee ff
ff
ff
ee ff
ii
dd
hh ll
ee ff
ff
Add without Carry
A
←
(A) + (M)
–
ff
ee ff
ii
Add Immediate Value (Signed) to SP
SP
←
(SP) + (16
M)
H:X
←
(H:X) + (16
M)
– – – – – – IMM
AIX #
opr
AND #
opr
AND
opr
AND
opr
AND
opr
,X
AND
opr
,X
AND ,X
AND
opr
,SP
AND
opr
,SP
ASL
opr
ASLA
ASLX
ASL
opr
,X
ASL ,X
ASL
opr
,SP
ASR
opr
ASRA
ASRX
ASR
opr
,X
ASR
opr
,X
ASR
opr
,SP
BCC
rel
Add Immediate Value (Signed) to H:X
– – – – – – IMM
AF
A4
B4
C4
D4
E4
F4
9EE4
9ED4
38
48
58
68
78
9E68
37
47
57
67
77
9E67
24
11
13
15
17
19
1B
1D
1F
25
27
ii
ii
dd
hh ll
ee ff
ff
2
2
3
4
4
3
2
4
5
4
1
1
4
3
5
4
1
1
4
3
5
3
4
4
4
4
4
4
4
4
3
3
Logical AND
A
←
(A) & (M)
0 – –
–
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
ff
ee ff
dd
Arithmetic Shift Left
(Same as LSL)
– –
ff
ff
dd
Arithmetic Shift Right
– –
ff
ff
rr
dd
dd
dd
dd
dd
dd
dd
dd
rr
rr
Branch if Carry Bit Clear
PC
←
(PC) + 2 + rel (C) = 0
– – – – – – REL
BCLR
n
,
opr
Clear Bit n in M
Mn
←
0
– – – – – –
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
BCS
rel
BEQ
rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
Branch if Greater Than or Equal To
(Signed Operands)
Branch if Greater Than (Signed
Operands)
Branch if Half Carry Bit Clear
Branch if Half Carry Bit Set
Branch if Higher
PC
←
(PC) + 2 +
rel
(C) = 1
PC
←
(PC) + 2 +
rel
(Z) = 1
– – – – – – REL
– – – – – – REL
BGE
opr
PC
←
(PC) + 2 +
rel
(N
⊕
V
) = 0
– – – – – – REL
90
rr
3
BGT
opr
PC
←
(PC) + 2 +
rel
(Z)
| (N
⊕
V
) = 0
– – – – – – REL
92
rr
3
BHCC
rel
BHCS
rel
BHI
rel
PC
←
(PC) + 2 +
rel
(H) = 0
PC
←
(PC) + 2 +
rel
(H) = 1
PC
←
(PC) + 2 +
rel
(C) | (Z) = 0
– – – – – – REL
– – – – – – REL
– – – – – – REL
28
29
22
rr
rr
rr
3
3
3
C
b0
b7
0
b0
b7
C