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| 型號(hào)： | MC68HC08JB8AADW |
| 廠商： | Motorola, Inc. |
| 英文描述： | This addendum provides additional information to the MC68HC908JB8 Technical Data, Rev. 2 |
| 中文描述： | 本增編提供了額外的資料MC68HC908JB8的技術(shù)數(shù)據(jù)，修訂版2 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 282K |
| 代理商： | MC68HC08JB8AADW |
HC908JB8AD/D
MC68HC08JB8A
MOTOROLA
Addendum to MC68HC908JB8 Technical Data
For More Information On This Product,
Go to: www.freescale.com
5
Memory
Characteristics
I/O ports Hi-Z leakage current
I
IL
—
—
±
10
μ
A
Input current
I
IN
—
—
±
1
μ
A
Capacitance
Ports (as input or output)
C
Out
C
In
—
—
—
—
12
8
pF
POR re-arm voltage
(6)
V
POR
0
—
100
mV
POR rise-time ramp rate
(7)
R
POR
0.035
—
—
V/ms
Monitor mode entry voltage
V
DD
+
V
HI
1.4
×
V
DD
2
×
V
DD
V
Pullup resistors
Port A, port B, port C, PTE0–PTE2, RST, IRQ
PTE3–PTE4 (with USB module disabled)
D– (with USB module enabled)
R
PU
25
4
1.2
40
5
1.5
55
6
2.0
k
LVI reset
V
LVR
2.8 (2.4)
3.3 (2.7)
3.8 (3.0)
(8)
V
1. V
DD
= 4.0 to 5.5 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25
°
C only.
3. Run (operating) I
DD
measured using external square wave clock source (f
XCLK
= 6 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 100 pF on all outputs. C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run I
DD
. Measured with all modules enabled.
4. Wait I
DD
measured using external square wave clock source (f
XCLK
= 6 MHz); all inputs 0.2 V from rail; no dc loads; less
than 100 pF on all outputs. C
L
= 20 pF on OSC2; 15 k
±
5% termination resistors on D+ and D– pins; all ports configured
as inputs; OSC2 capacitance linearly affects wait I
DD
5. STOP I
DD
measured with USB in suspend mode; OSC1 grounded; transceiver pullup resistor of 1.5 k
±
5% between V
REG
and D– pins and 15 k
±
5% termination resistor on D+ pin; no port pins sourcing current.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum V
REG
is not reached before the internal POR reset is released, RST must be driven low externally until minimum
V
REG
is reached.
8. The numbers in parenthesis are MC68HC08JB8 (non-A part) values.
Table 2. DC Electrical Characteristics
Characteristic
(1)
Symbol
Min
Typ
(2)
Max
Unit
Table 3. Memory Characteristics
Characteristic
Symbol
Min
Max
Unit
RAM data retention voltage
V
RDR
1.3
—
V
Notes:
Since MC68HC08JB8A is a ROM device, FLASH memory electrical characteristics do not apply.
F
Freescale Semiconductor, Inc.
n
.
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| MC68HC08JB8AJDW | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:This addendum provides additional information to the MC68HC908JB8 Technical Data, Rev. 2 |
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