
Functional Description
MC68HC08GR32A MC68HC08GR16A Data Sheet, Rev. 0
Freescale Semiconductor
227
18.3.2 Input Capture
An input capture function has three basic parts: edge select logic, an input capture latch, and a 16-bit
counter. Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value
of the free-running counter after the corresponding input capture edge detector senses a defined
transition. The polarity of the active edge is programmable. The level transition which triggers the counter
transfer is defined by the corresponding input edge bits (ELSxB and ELSxA in T2SC0 through T2SC5
control registers with x referring to the active channel number). When an active edge occurs on the pin of
an input capture channel, the TIM2 latches the contents of the TIM2 counter into the TIM2 channel
registers, T2CHxH:T2CHxL. Input captures can generate TIM2 CPU interrupt requests. Software can
$0458
TIM2 Channel 2 Register Low
(T2CH2L)
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Indeterminate after reset
$0459
TIM2 Channel 3 Status and Con-
trol Register (T2SC3)
Read:
CH3F
CH3IE
0
MS3A
ELS3B
ELS3A
TOV3
CH3MAX
Write:
0
Reset:
0
$045A
TIM2 Channel 3 Register High
(T2CH3H)
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
Indeterminate after reset
$045B
TIM2 Channel 3 Register Low
(T2CH3L
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Indeterminate after reset
$045C
TIM2 Channel 4 Status and Con-
trol Register (T2SC4)
Read:
CH4F
CH4IE
0
MS4A
ELS4B
ELS4A
TOV4
CH4MAX
Write:
0
Reset:
0
$045D
TIM2 Channel 4 Register High
(T2CH4H)
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
Indeterminate after reset
$045E
TIM2 Channel 4 Register Low
(T2CH4L)
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Indeterminate after reset
$045F
TIM2 Channel 5 Status and Con-
trol Register (T2SC5)
Read:
CH5F
CH5IE
0
MS5A
ELS5B
ELS5A
TOV5
CH5MAX
Write:
0
Reset:
0
$0460
TIM2 Channel 5 Register High
(T2CH5H)
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
Indeterminate after reset
$0461
TIM2 Channel 5 Register Low
(T2CH5L)
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Indeterminate after reset
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented
Figure 18-3. TIM2 I/O Register Summary (Sheet 2 of 2)