Instruction Set Summary
MC68HC08GP32A MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor
77
BHS rel
Branch if Higher or Same
(Same as BCC)
PC
← (PC) + 2 + rel ? (C) = 0
–––– –– REL
24
rr
3
BIH rel
Branch if IRQ Pin High
PC
← (PC) + 2 + rel ? IRQ = 1
–––– –– REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC
← (PC) + 2 + rel ? IRQ = 0
–––– –– REL
2E
rr
3
BIT #opr
BIT opr
BIT opr,X
BIT ,X
BIT opr,SP
Bit Test
(A) & (M)
0 – –
–
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A5
B5
C5
D5
E5
F5
9EE5
9ED5
ii
dd
hh ll
ee ff
ff
ee ff
2
3
4
3
2
4
5
BLE opr
Branch if Less Than or Equal To
(Signed Operands)
PC
← (PC) + 2 + rel ? (Z) | (N
⊕ V) = 1 –––– –– REL
93
rr
3
BLO rel
Branch if Lower (Same as BCS)
PC
← (PC) + 2 + rel ? (C) = 1
–––– –– REL
25
rr
3
BLS rel
Branch if Lower or Same
PC
← (PC) + 2 + rel ? (C) | (Z) = 1
–––– –– REL
23
rr
3
BLT opr
Branch if Less Than (Signed Operands)
PC
← (PC) + 2 + rel ? (N
⊕ V) =1
–––– –– REL
91
rr
3
BMC rel
Branch if Interrupt Mask Clear
PC
← (PC) + 2 + rel ? (I) = 0
–––– –– REL
2C
rr
3
BMI rel
Branch if Minus
PC
← (PC) + 2 + rel ? (N) = 1
–––– –– REL
2B
rr
3
BMS rel
Branch if Interrupt Mask Set
PC
← (PC) + 2 + rel ? (I) = 1
–––– –– REL
2D
rr
3
BNE rel
Branch if Not Equal
PC
← (PC) + 2 + rel ? (Z) = 0
–––– –– REL
26
rr
3
BPL rel
Branch if Plus
PC
← (PC) + 2 + rel ? (N) = 0
–––– –– REL
2A
rr
3
BRA rel
Branch Always
PC
← (PC) + 2 + rel
–––– –– REL
20
rr
3
BRCLR n,opr,rel Branch if Bit n in M Clear
PC
← (PC) + 3 + rel ? (Mn) = 0
–––– –
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
5
BRN rel
Branch Never
PC
← (PC) + 2
–––– –– REL
21
rr
3
BRSET n,opr,rel Branch if Bit n in M Set
PC
← (PC) + 3 + rel ? (Mn) = 1
–––– –
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
5
BSET n,opr
Set Bit n in M
Mn
← 1
–––– ––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
4
BSR rel
Branch to Subroutine
PC
← (PC) + 2; push (PCL)
SP
← (SP) – 1; push (PCH)
SP
← (SP) – 1
PC
← (PC) + rel
–––– –– REL
AD
rr
4
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
Compare and Branch if Equal
PC
← (PC) + 3 + rel ? (A) – (M) = $00
PC
← (PC) + 3 + rel ? (A) – (M) = $00
PC
← (PC) + 3 + rel ? (X) – (M) = $00
PC
← (PC) + 3 + rel ? (A) – (M) = $00
PC
← (PC) + 2 + rel ? (A) – (M) = $00
PC
← (PC) + 4 + rel ? (A) – (M) = $00
–––– ––
DIR
IMM
IX1+
IX+
SP1
31
41
51
61
71
9E61
dd rr
ii rr
ff rr
rr
ff rr
5
4
5
4
6
CLC
Clear Carry Bit
C
← 0
–––– –0 INH
98
1
CLI
Clear Interrupt Mask
I
← 0
––0– –– INH
9A
2
Table 6-1. Instruction Set Summary (Sheet 2 of 6)
Source
Form
Operation
Description
Effect
on CCR
Addre
s
Mode
Op
co
de
Op
era
n
d
C
y
cl
es
VH I N Z C