
I/O Ports
MC68HC08AZ60 — Rev 1.0
280
I/O Ports
MOTOROLA
Fifty bidirectional input/output (I/O) form seven parallel ports. All I/O pins
are programmable as inputs or outputs.
NOTE:
Connect any unused I/O pins to an appropriate logic level, either VDD or
VSS. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Addr.
Register Name
Bit 7
65
4321
Bit 0
$0000
Port A Data Register (PTA)
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
$0001
Port B Data Register (PTB)
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
$0002
Port C Data Register (PTC)
0
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
$0003
Port D Data Register (PTD)
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
$0004
Data Direction Register A (DDRA) DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
$0005
Data Direction Register B (DDRB) DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
$0006
Data Direction Register C (DDRC) MCLKEN
0
DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
$0007
Data Direction Register D (DDRD) DDRD7
DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
$0008
Port E Data Register (PTE)
PTE7
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
$0009
Port F Data Register (PTF)
0
PTF6
PTF5
PTF4
PTF3
PTF2
PTF1
PTF0
$000A
Port G Data Register (PTG)
0
PTG2
PTG1
PTG0
$000B
Port H Data Register (PTH)
0
PTH1
PTH0
$000C
Data Direction Register E (DDRE) DDRE7
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
$000D
Data Direction Register F (DDRF)
0
DDRF6
DDRF5
DDRF4
DDRF3
DDRF2
DDRF1
DDRF0
$000E
Data Direction Register G (DDRG)
0
DDRG2 DDRG1 DDRG0
$000F
Data Direction Register H (DDRH)
0
DDRH1‘ DDRH0
Figure 1. CAN Protocol I/O Port Register Summary
2-ioports
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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