
Data Sheet
MC68HC08AS32 — Rev. 4.1
266
Freescale Semiconductor
17.5 Control Timing
17.6 ADC Characteristics
Characteristic(1)
Symbol
Min
Max
Unit
Bus operating frequency (4.5–5.5 V — VDD only)
fBUS
—8.4
MHz
RST pulse width low
tRL
1.5
—
tCYC
IRQ interrupt pulse width low (edge-triggered)
tILHI
1.5
—
tCYC
IRQ interrupt pulse period
tILIL
(2)
—
tCYC
EEPROM programming time per byte
tEEPGM
10
—
ms
EEPROM erasing time per byte
tEBYTE
10
—
ms
EEPROM erasing time per block
tEBLOCK
10
—
ms
EEPROM erasing time per bulk
tEBULK
10
—
ms
EEPROM programming voltage discharge period
tEEFPV
100
—
s
16-bit timer(3)
Input capture pulse width(2)
Input capture period
tTH, tTL
tTLTL
2
(4)
—
tCYC
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +105°C, unless otherwise noted.
3. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
4. The minimum period tTLTL or tILIL should not be less than the number of cycles it takes to execute the capture interrupt service
routine plus 1 tCYC.
Characteristic
Min
Max
Unit
Comments
Resolution
8
Bits
Absolute accuracy
(VREFL = 0 V, VDDA = VREFH = 5 V ± 10%)
–1
+1
LSB
Includes quantization
Conversion range(1)
VREFL
VREFH
V
VREFL = VSSA
Power-up time
16
17
s
Conversion time period
Input leakage(2) (3) ports B and D
—
± 1
A
Conversion Time
16
17
ADC clock cycles
Includes sampling time
Monotonicity
Inherent within total error
Zero input reading
00
01
Hex
VIN = VREFL
Full-scale reading
FE
FF
Hex
VIN = VREFH
Sample time(2) (3)
5
—
ADC clock cycles
Input capacitance
—
8
pF
Not tested
ADC internal clock
500 k
1.048 M
Hz
Tested only at 1 MHz
Analog input voltage
–0.3
VDD + 0.3
V
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, VDDA/VDDAREF = 5.0 Vdc ± 10%, VSSA = 0 Vdc, VREFH = 5.0 Vdc ± 10%
2. The external system error caused by input leakage current is approximately equal to the product of R source and input current.
3. Source impedances greater than 10 k
adversely affect internal RC charging time during input sampling.