參數(shù)資料
型號(hào)： MC68HC08AS20FNR2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, MICROCONTROLLER, PQCC52
封裝： PLASTIC, LCC-52
文件頁(yè)數(shù)： 38/96頁(yè)
文件大?。?/td> 3243K
代理商： MC68HC08AS20FNR2
4
MC68HC05E0
MOTOROLA
4-7
RESETS, INTERRUPTS AND LOW POWER MODES
4.2.2
Non-Maskable Software interrupt (SWI)
The software interrupt SWI is an executable instruction and a non-maskable interrupt: it is
executed regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts enabled), SWI
is executed after interrupts which were pending when the SWI was fetched, but before interrupts
generated after the SWI was fetched. The SWI interrupt service routine address is specied by
the contents of memory locations $FFFC and $FFFD.
4.2.3
Maskable Hardware Interrupts
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and external) are
disabled. Clearing the I bit enables interrupts.
Note:
The internal interrupt latch is cleared in the rst part of the interrupt service routine;
therefore, one external interrupt pulse could be latched and serviced as soon as the I
bit is cleared.
4.2.3.1
External Interrupt (INTX)
The interrupt request is latched immediately following the selected edge on the INTX pin. It is then
synchronized internally and serviced by the routine that has its start address contained in memory
locations $FFFA and $FFFB. The External Interrupt Mask bit (INTMX) in the Interrupt Control
Register ($000E) allows this interrupt to be masked from the processor.
4.2.3.2
Real Time Interrupt
The interrupt request is latched when the Real Time Interrupt Timer times out. It is then
synchronized internally and serviced by the routine that has its start address contained in memory
locations $FFFA and $FFFB. The Real Time Interrupt Enable bit (RTIE) in the RTI Control Register
($0018) allows this interrupt to be masked from the processor.
4.2.3.3
Port C Wake-up
The interrupt request is latched when a dened Wake-up signal appears on one of the pins of Port
C. It is then synchronized internally and serviced by the routine that has its start address contained
in memory locations $FFFA and $FFFB. The Wake-up Enable bits (WEn) in the Wake-up Enable
Register ($0013) allow these interrupts to be masked from the processor.
43
相關(guān)PDF資料
PDF描述
MC68HC08AS20VFNR2 8-BIT, MROM, MICROCONTROLLER, PQCC52
MC68HC08AS20CFN 8-BIT, MROM, MICROCONTROLLER, PQCC52
MC68HC08AZ48AVFU 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PQFP64
MC68HC08AZ60FU 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PQFP64
MC68HC08AZ60FU 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PQFP64
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68HC08AZ0 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Advance Information
MC68HC08AZ0CFU 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Advance Information
MC68HC08AZ16 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Microcontroller Unit
MC68HC08AZ24 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Microcontroller Unit
MC68HC08AZ32 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Advance Information
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*