MOTOROLA
10-12
MC68HC05X16
Rev. 1
RESETS AND INTERRUPTS
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Error IRQ:
this is set when either the error status or bus status bits in the MCAN status register
Data overrun: an incoming message on the bus cannot be received because both receive buffers
are tied up.
Wake-up IRQ: this signals activity on the bus while the MCAN is in SLEEP mode. This is the only
nonmaskable CIRQ.
CIRQ interrupts are serviced by the routine located at the address specied by the contents of
$3FF0 and $3FF1.
10.2.3.4
Timer interrupts
There are ve different timer interrupt ags (ICF1, ICF2, OCF1, OCF2 and TOF) that will cause a
timer interrupt whenever they are set and enabled. These ve interrupt ags are found in the ve
most signicant bits of the timer status register (TSR) at location $0013. ICF1 and ICF2 will vector
to the service routine dened by $3FF8-$3FF9, OCF1 and OCF2 will vector to the service routine
dened by $3FF6–$3FF7 and TOF will vector to the service routine dened by $3FF4–$3FF5 as
There are three corresponding enable bits; ICIE for ICF1 and ICF2, OCIE for OCF1 and OCF2,
and TOIE for TOF. These enable bits are located in the timer control register (TCR) at address
10.2.3.5
Serial communications interface (SCI) interrupts
There are ve different interrupt ags (TDRE, TC, OR, RDRF and IDLE) that cause SCI interrupts
whenever they are set and enabled. These ve interrupt ags are found in the ve most signicant
bits of the SCI status register (SCSR) at location $0010.
There are four corresponding enable bits: TIE for TDRE, TCIE for TC, RIE for OR and RDRF, and
ILIE for IDLE. These enable bits are located in the serial communications control register 2
The SCI interrupt causes the program counter to vector to the address pointed to by memory
locations $3FF2 and $3FF3 which contain the starting address of the interrupt service routine.
Software in the SCI interrupt service routine must determine the priority and cause of the interrupt
by examining the interrupt ags and the status bits located in the serial communications status
register SCSR (address $0010).
The general sequence for clearing an interrupt is a software sequence of accessing the serial
communications status register while the ag is set followed by a read or write of an associated
register. Refer to
Section 7 for a description of the SCI system and its interrupts.
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