
MC68HC05X16
Rev. 1
SERIAL COMMUNICATIONS INTERFACE
7
7.12
Baud rate selection
The exibility of the baud rate generator allows many different baud rates to be selected, depending
on the CPU clock frequency. A particular baud rate may be generated by manipulating the various
prescaler and division ratio bits. Table 7-6, Table 7-7 and Table 7-8 show the highest baud rates that can be achieved for ve typical crystal frequencies, for each of the CPU clock frequency options and
only using the prescaler bits. Table 7-9 shows how lower transmitter or receiver baud rates may be
obtained using a further division ratio provided by the SCI rate select bits. Note that the ve
examples given in Table 7-9 are representative samples only.
Note:
The clock in the ‘Clock divided by’ column refers to the internal processor clock.
Table 7-6 SCI baud rate selection with CPU clock frequency = fOSC/2
Clock
divided
by
Crystal frequency – fosc (MHz)
SCP1
SCP0
4.194304
4.00
2.4576
2.00
1.8432
0
1
131072
125000
76800
62500
57600
0
1
3
43691
41667
25600
20833
19200
1
0
4
32768
31250
19200
15625
14400
1
13
10082
9600
5907
4800
4430
Table 7-7 SCI baud rate selection with CPU clock frequency = fOSC/8
Clock
divided
by
Crystal frequency – fosc (MHz)
SCP1
SCP0
16.00
8.00
4.9152
4.194304
2.4576
0
1
125000
62500
38400
32768
19200
0
1
3
41667
20833
12800
10082
14400
1
0
4
31250
15625
9600
8192
4430
1
13
9600
4800
2954
2521
1477
Table 7-8 SCI baud rate selection with CPU clock frequency = fOSC/10
Clock
divided
by
Crystal frequency – fosc (MHz)
SCP1
SCP0
20.00
18.432
10.00
6.144
5.0
0
1
125000
115200
62500
38400
31250
0
1
3
41667
38400
20833
12800
10417
1
0
4
31250
28800
15625
9600
7813
1
13
9600
8861
4800
2954
2400
120
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com