MOTOROLA
vi
MC68HC05X16
Rev. 1
INDEX
CINT – MCAN interrupt register
5-12
EIF – error interrupt flag
5-12
OIF – overrun interrupt flag
5-12
RIF – receive interrupt flag
5-13
TIF – transmit interrupt flag
5-12
WIF – wake-up interrupt flag
5-12
CIRQ
10-11
clocks – see oscillator clock
COCNTRL – MCAN output control register
5-18
OCM1, OCM0 – output control mode bits
5-18
COCO bit in ADSTAT
9-4
COMPSEL bit in CCOM
5-8
COP
10-3
block diagram
10-4
COS bit in CCOM
5-9
counter
6-1
alternate counter register
6-3
counter register
6-3
CPHA bit in SCCR1
7-12
CPOL bit in SCCR1
7-12
CPU
A – accumulator
11-1
addressing modes
11-11
–
11-13
CCR – condition code register
11-2
instruction set
11-3
11-10
PC – program counter
11-2
programming model
11-1
SP – stack pointer
11-2
stacking order
11-2
X – index register
11-2
crystal
2-13
CSTAT – MCAN status register
5-10
BS – bus status bit
5-10
DO – data overrun bit
5-11
ES – error status bit
5-10
RBS – receive buffer status bit
5-11
RS – receive status bit
5-10
TBA – transmit buffer access bit
5-11
TCS – transmission complete status bit
5-11
TS – transmit status bit
5-10
D
DB7-DB0 bits in TDS
5-21
direct addressing mode
11-11
DIV2, DIV8 bits in MOR
B-12
DLC3-DLC0 bits in TRTDL
5-20
DO bit in CSTAT
5-11
E
E1ERA bit in EEPROM control
3-5
E1LAT bit in EEPROM control
3-5
E1PGM bit in EEPROM control
3-5
E6LAT bit in EEPROM control
B-9
E6PGM bit in EEPROM control
B-9
ECLK bit in EEPROM control
3-5
4-3
EE1P bit in OPTR
3-8
,
B-11
EEPROM
erase operation
3-6
programming operation
3-7
read operation
3-6
EEPROM control register
3-4
,
B-8
CAF – MCAN asleep flag
B-8
E1ERA – erase/programming bit
3-5
E1LAT – programming latch enable bit
3-5
E1PGM – charge pump enable/disable bit
3-5
E6LAT – EPROM program latch enable bit
B-9
E6PGM – EPROM program enable bit
B-9
ECLK – external clock option bit
3-5
,
4-3
WOIE – wired-OR interrupt enable bit
B-8
EIE bit in CCNTRL
5-6
EIF bit in CINT
5-12
EPROM
MOR
B-12
program operation
B-8
read operation
B-7
ES bit in CSTAT
5-10
extended addressing mode
11-12
external clock
2-13
F
FE bit in SCSR
7-17
flow charts
interrupts
10-8
self check mode (MC68HC05X16)
2-2
STOP and WAIT
2-9
FOLV2, FOLV1 bits in TCR
6-5
H
H-bit in CCR
11-2
I
I-bit in CCR
11-3
ICF1, ICF2 bits in TSR
6-6
ICIE bit in TCR
6-4
ICR1, ICR2 – input capture registers
6-7
ID10-ID3 bits in TBI
5-20
ID2-ID0 bits in TRTDL
5-20
IDLE bit in SCSR
7-16
IEDG1 bit in TCR
6-5
ILIE bit in SCCR2
7-14
immediate addressing mode
11-11
indexed addressing modes
11-12
inherent addressing mode
11-11
input capture
6-7
instruction set
11-3
–
11-10
tables of instructions
11-5
–
11-10
INTE bit in Miscellaneous
3-11
,
10-10
interrupts