參數資料
型號： MC68HC05V7CFU
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP64
封裝： QFP-64
文件頁數： 132/170頁
文件大?。?/td> 980K
代理商： MC68HC05V7CFU
MOTOROLA
SECTION 7: POWER SUPPLY AND REGULATION
Page 50
MC68HC05V7 Specification Rev. 1.0
NOTE:
If the LVR option is enabled, reset will be asserted when VDD drops to the
appropriate level.
NOTE:
Before the PDC bit is written to a 0, the state of the IGNS bit should be
debounced in software. This will ensure that the primary regulator does
not power up with any bounce that may be present on Vign.
7.4.1
MASK OPTIONS
The regulator has three mask options associated with it. The first one is the MDLCPU
option. If this option is enabled, a rising edge on the MDLC BUS pin or the VIGN pin can
bring the primary regulator out of the Standby power mode. If this option is not enabled,
only the VIGN pin will bring the primary regulator out of the Standby power mode.
The second mask option is the VDDC option. This option, if enabled, will enable an active
pulldown device, connected between VDD and VSS, to turn on when the primary regulator
is disabled. This option should not be selected if an external voltage regulator is being used.
The third mask option is the regulator enable option. If it is not desired to use the on-board
voltage regulator, this option should not be selected. In this case the secondary regulator
will still remain active in order to properly keep the primary regulator turned off. While the
regulator is not enabled the MDLCPU option will remain operational but will serve no
purpose. The VDDC option and the MISCELLANEOUS register will continue to operate
normally. The VDDC function (VDD to VSS clamping device) uses the PDC bit to determine
when to turn the clamping device on. If this option is enabled and the PDC bit is written to
a "0", the clamping device will turn on. It will not turn off until a rising edge is detected on
VIGN or a rising edge on the BUS pin is detected provided the MDLCPU option is selected.
If the configuration shown in Figure 7-4 is used with the regulator enable option selected,
the MDLCPU and VDDC options may be selected. In addition, software must write a ’1’ to
the PDC bit in the miscellaneous register to initialize it after power-up. This prevents read-
modify-write instructions to the MISCELLANEOUS register from accidentally clearing the
PDC bit.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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