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參數(shù)資料
| 型號： | MC68HC05RC18FN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 63/126頁 |
| 文件大?。?/td> | 1180K |
| 代理商： | MC68HC05RC18FN |
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Interrupts
MC68HC05RC18 — Rev. 2.1
General Release Specification
Freescale Semiconductor
Interrupts
41
NON-DISCLOSURE
AGREEMENT
REQUIRED
4.4 Reset Interrupt Sequence
The reset function is not in the strictest sense an interrupt; however, it is
acted upon in a similar manner as shown in Figure 4-1. A low-level input
on the RESET pin or an internally generated RST signal, causes the
program to vector to its starting address, which is specified by the
contents of memory locations $3FFE and $3FFF. The I bit in the
condition code register is also set. The MCU is configured to a known
state during this type of reset.
4.5 Software Interrupt (SWI)
The SWI is an executable instruction and a nonmaskable interrupt since
it is executed regardless of the state of the I bit in the CCR. If the I bit is
zero (interrupts enabled), the SWI instruction executes after interrupts
that were pending before the SWI was fetched or before interrupts
generated after the SWI was fetched. The interrupt service routine
address is specified by the contents of memory locations $3FFC and
$3FFD.
Table 4-1. Vector Address for Interrupts and Reset
Register
Flag
Name
Interrupt
CPU Interrupt
Vector
Address
N/A
Reset
RESET
$3FFE–$3FFF
N/A
Software Interrupt
SWI
$3FFC–$3FFD
N/A
External Interrupts*
IRQ
$3FFA–$3FFB
MCSR
EOC
End of Cycle Interrupt
CMT
$3FF8–$3FF9
CTCSR
CTOF,
RTIF
Real Time Interrupt
Core Timer Overflow
CORE TIMER
$3FF6–$3FF7
*External interrupts include IRQ and port B keyscan sources.
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