參數(shù)資料
型號(hào): MC68HC05P4ADWR3
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: PLASTIC, SOIC-28
文件頁(yè)數(shù): 64/102頁(yè)
文件大?。?/td> 930K
代理商: MC68HC05P4ADWR3
Advance Information
MC68HC05P4A — Rev. 6.0
64
Timer
MOTOROLA
Timer
Accessing the timer status register satisfies the first condition required
to clear status bits. The remaining step is to access the register
corresponding to the status bit.
A problem can occur when using the timer overflow function and reading
the free-running counter at random times to measure an elapsed time.
Without incorporating the proper precautions into software, the timer
overflow flag could unintentionally be cleared if:
1. The timer status register is read or written when TOF is set, and
2. The LSB of the free-running counter is read but not for the purpose
of servicing the flag.
The counter alternate register at address $1A and $1B contains the
same value as the free-running counter (at address $18 and $19);
therefore, this alternate register can be read at any time without affecting
the timer overflow flag in the timer status register.
8.8 Timer During Wait or Halt Mode
The CPU clock halts during the wait or halt mode, but the timer remains
active. If interrupts are enabled, a timer interrupt will cause the
processor to exit the wait mode.
8.9 Timer During Stop Mode
In stop mode, the timer stops counting and holds the last count value if
stop is exited by an interrupt. If RESET is used, the counter is forced to
$FFFC. During stop, if at least one valid input capture edge occurs at
the TCAP pin, the input capture detect circuit is armed. This does not
set any timer flags to wake up the MCU, but when the MCU does wake
up, there is an active input capture flag and data from the first valid edge
that occurred during stop mode. If RESET is used to exit stop mode,
then no input capture flag or data remains, even if a valid input capture
edge occurred.
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