參數(shù)資料
型號: MC68HC05P4ADWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: PLASTIC, SOIC-28
文件頁數(shù): 80/102頁
文件大?。?/td> 930K
代理商: MC68HC05P4ADWR2
Instruction Set
Instruction Set Summary
MC68HC05P4A — Rev. 6.0
Advance Information
MOTOROLA
Instruction Set
79
BRCLR n opr rel
Branch if bit n clear
PC
← (PC) + 2 + rel ? Mn = 0
————
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
5
BRSET n opr rel
Branch if Bit n Set
PC
← (PC) + 2 + rel ? Mn = 1
————
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
5
BRN rel
Branch Never
PC
← (PC) + 2 + rel ? 1 = 0
—————
REL
21
rr
3
BSET n opr
Set Bit n
Mn
← 1
—————
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
5
BSR rel
Branch to
Subroutine
PC
← (PC) + 2; push (PCL)
SP
← (SP) – 1; push (PCH)
SP
← (SP) – 1
PC
← (PC) + rel
—————
REL
AD
rr
6
CLC
Clear Carry Bit
C
← 0
———— 0
INH
98
2
CLI
Clear Interrupt Mask
I
← 0
— 0 — — —
INH
9A
2
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
Clear Byte
M
← $00
A
← $00
X
← $00
M
← $00
M
← $00
—— 0
1 —
DIR
INH
IX1
IX
3F
4F
5F
6F
7F
dd
ff
5
3
6
5
CMP #opr
CMP opr
CMP opr,X
CMP ,X
Compare
Accumulator with
Memory Byte
(A) – (M)
— —
IMM
DIR
EXT
IX2
IX1
IX
A1
B1
C1
D1
E1
F1
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
Table 11-6. Instruction Set Summary (Continued)
Source
Form
Operation
Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
HIN Z C
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