- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69027 > MC68HC05P4ADWE (FREESCALE SEMICONDUCTOR INC) 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 PDF資料下載
參數(shù)資料
| 型號： | MC68HC05P4ADWE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 32/72頁 |
| 文件大?。?/td> | 400K |
| 代理商： | MC68HC05P4ADWE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁當(dāng)前第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
Timer
MC68HC05P4A Data Sheet, Rev. 7.1
38
Freescale Semiconductor
TOIE — Timer Overflow Interrupt Enable Bit
1 = Interrupt enabled
0 = Interrupt disabled
IEDG — Input Edge Bit
Value of input edge determines which level transition on TCAP pin will trigger free-running counter
transfer to the input capture register. Reset does not affect the IEDG bit.
1 = Positive edge
0 = Negative edge
OLVL — Output Level Bit
Value of output level is clocked into output level register by the next successful output compare and
will appear on the TCMP pin.
1 = High output
0 = Low output
Bits 2, 3, and 4 — Not used
Always read 0
8.6 Timer Status Register
The timer status register (TSR) is a read-only register containing three status flag bits.
ICF — Input Capture Flag Bit
1 = Flag set when selected polarity edge is sensed by input capture edge detector
0 = Flag cleared when TSR and input capture low register ($15) are accessed
OCF — Output Compare Flag Bit
1 = Flag set when output compare register contents match the free-running counter contents
0 = Flag cleared when TSR and output compare low register ($17) are accessed
TOF — Timer Overflow Flag Bit
1 = Flag set when free-running counter transition from $FFFF to $0000 occurs
0 = Flag cleared when TSR and counter low register ($19) are accessed
Bits 0–4 — Not used
Always read 0
Accessing the timer status register satisfies the first condition required to clear status bits. The remaining
step is to access the register corresponding to the status bit.
Address:
$0013
Bit 7
654321
Bit 0
Read:
ICF
OCF
TOF
00000
Write:
Reset:
U
00000
= Unimplemented
Figure 8-3. Timer Status Register (TSR)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC05P4APE | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| MC68HC05P4ADW | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC05P6VS | 8-BIT, 2.1 MHz, MICROCONTROLLER, CDIP28 |
| MC68HC05P6CS | 8-BIT, 2.1 MHz, MICROCONTROLLER, CDIP28 |
| MC68HC05P6VP | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05P4DW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC05P4P | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC05P6 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC05P6_1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC05P8 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。