參數(shù)資料
型號(hào)： MC68HC05P18MDWR3
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 83/144頁
文件大?。?/td> 1348K
代理商： MC68HC05P18MDWR3
Interrupts
Interrupt Types
MC68HC(8)05P18 — Rev. 2.0
Advance Information
MOTOROLA
Interrupts
43
4.3 Interrupt Types
The interrupts fall into three categories:
Reset
Software
Hardware
4.3.1 Reset Interrupt Sequence
The reset function is not in the strictest sense an interrupt; however, it is
acted upon in a similar manner as shown in Figure 4-1. A low level input
on the RESET pin or internally generated RST signal causes the
program to vector to its starting address which is specified by the
contents of memory locations $3FFE and $3FFF. The I bit in the
condition code register is also set. The MCU is configured to a known
state during this type of reset as described in Section 5. Resets.
4.3.2 Software Interrupt (SWI)
The SWI is an executable instruction. It is also a non-maskable interrupt
since it is executed regardless of the state of the I bit in the CCR. As with
any instruction, interrupts pending during the previous instruction will be
serviced before the SWI opcode is fetched. The interrupt service routine
address for the SWI instruction is specified by the contents of memory
locations $3FFC and $3FFD.
4.3.3 Hardware Interrupts
All hardware interrupts are maskable by the I bit in the CCR. If the I bit
is set, all hardware interrupts (internal and external) are disabled.
Clearing the I bit enables the hardware interrupts. Four hardware
interrupts are explained here.
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