參數(shù)資料
型號: MC68HC05P18AMP
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28
封裝: PLASTIC, DIP-28
文件頁數(shù): 111/130頁
文件大?。?/td> 1310K
代理商: MC68HC05P18AMP
Serial Input/Output Ports (SIOP)
SIOP Registers
MC68HC05P18A
Technical Data
Serial Input/Output Ports (SIOP)
NON-DISCLOSURE
AGREEMENT
REQUIRED
SPE — Serial Peripheral Enable Bit
When set, the SPE bit enables the SIOP subsystem such that
SDO/PB5 is the serial data output, SDI/PB6 is the serial data input,
and SCK/PB7 is a serial clock input in the slave mode or a serial clock
output in the master mode. The port B DDR and data registers can be
manipulated as usual (except for PB5); however, these actions could
affect the transmitted or received data.
The SPE bit is readable and writable at any time. Clearing the SPE bit
while a transmission is in progress will:
1. Abort the transmission
2. Reset the serial bit counter
3. Convert the port B/SIOP port to a general-purpose I/O port
Reset clears the SPE bit.
MSTR — Master Mode Select Bit
When set, the MSTR bit configures the serial I/O port for master
mode. A transfer is initiated by writing to the SDR. Also, the SCK pin
becomes an output providing a synchronous data clock dependent
upon the oscillator frequency. When the device is in slave mode, the
SDO and SDI pins do not change function. These pins behave exactly
the same in both the master and slave modes.
The MSTR bit is readable and writable at any time regardless of the
state of the SPE bit. Clearing the MSTR bit will abort any transfers that
may have been in progress. Reset clears the MSTR bit, placing the
SIOP subsystem in slave mode.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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