參數(shù)資料
型號(hào): MC68HC05K3DWR2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO16
封裝: SOIC-16
文件頁(yè)數(shù): 86/132頁(yè)
文件大?。?/td> 1188K
代理商: MC68HC05K3DWR2
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Operational Modes
PEEPROM Serial Programming Mode
MC68HC05K3 — Revision 4.0
Technical Data
MOTOROLA
Operational Modes
57
IRQ status/control register so that the IRQ external interrupt is enabled.
All other registers, memory, and input/output lines remain in their
previous states.
If timer interrupts are enabled, a timer interrupt causes the processor to
exit wait mode and resume normal operation. Thus, the timer can be
used to generate a periodic exit from wait mode. Wait mode also is
exited when an external IRQ or RESET occurs.
6.3.4 COP Watchdog Timer Considerations
If the COP watchdog timer is enabled by the mask option, any execution
of the STOP instruction (either intentional or inadvertent due to the CPU
being disturbed) causes the oscillator to halt and prevent the COP
watchdog timer from timing out unless the STOP instruction is disabled
by a mask option.
If the mask option is selected to enable the COP watchdog timer, the
COP resets the MCU when it times out. Therefore, it is recommended
that the mask option be selected to disable the COP watchdog for a
system that must have intentional uses of the wait mode for periods
longer than the COP timeout period.
6.4 PEEPROM Serial Programming Mode
The internal personality EEPROM (PEEPROM) can be erased, read, or
programmed through the application of serial data patterns to the IRQ
and PB0 pins, if the PEEPROM serial programming mode is selected
following reset. Refer to 9.6 PEEPROM Serial Programming for details.
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