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參數(shù)資料
| 型號(hào)： | MC68HC05K3CSD |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SSOP-16 |
| 文件頁數(shù)： | 96/132頁 |
| 文件大?。?/td> | 2612K |
| 代理商： | MC68HC05K3CSD |
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Technical Data
MC68HC05K3 — Rev. 5
Parallel Input/Output (I/O)
Parallel Input/Output (I/O)
7.4.4 Port B with 3-Pin RC Oscillator
The PB1/OSC3 pin may be used as an output from a 3-pin RC oscillator
when the mask option for a 3-pin RC oscillator is used. In this case, the
following conditions apply:
The PB1 data register bit can be used as a read/write storage
location without affecting the oscillator. PB1 is unaffected by reset.
The DDRB1 data direction bit can be used as a read/write storage
location without affecting the oscillator. DDRB1 is cleared by
reset.
The software programmable pulldown on PB1/OSC3 is disabled,
regardless of the mask option selection for the software
programmable pulldowns or the state of PDRB1.
7.5 I/O Port Programming
All I/O pins can be programmed as inputs or outputs, with or without
pulldown devices.
7.5.1 Pin Data Direction
The direction of a pin is determined by the state of its corresponding bit
in the associated port data direction register (DDR). A pin is configured
as an output if its corresponding DDR bit is set to a logic 1. A pin is
configured as an input if its corresponding DDR bit is cleared to a logic 0.
The data direction bits DDRB0, DDRB1, and DDRA0–DDRA7 are
read/write bits that can be manipulated with read-modify-write
instructions. At power-on or reset, all DDRs are cleared, which
configures all port pins as inputs. If the mask option for software
programmable pulldowns is selected, all pins initially power-up with their
software programmable pulldowns enabled.
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Freescale Semiconductor, Inc.
For More Information On This Product,
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ARCHIVED
BY
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SEMICONDUCT
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2006
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