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參數(shù)資料
| 型號(hào)： | MC68HC05K3CDW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 53/132頁 |
| 文件大?。?/td> | 2612K |
| 代理商： | MC68HC05K3CDW |
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General Description
Functional Pin Description
MC68HC05K3 — Rev. 5
Technical Data
General Description
inverted. The edge or level sensitivity selected by the mask option for the
IRQ pin also applies to the I/O pins ORed to create an IRQ signal.
The IRQ pin contains an internal Schmitt trigger to improve noise
immunity. For more details, see Section 4. Interrupts.
1.7.5 PA0–PA7
These eight I/O lines comprise port A. The state of any pin is software
programmable and all port A lines are configured as inputs during
power-on or reset, except in serial program mode. The four upper-order
I/O pins (PA4–PA7) are capable of sinking higher currents. The four
lower-order I/O pins (PA0–PA3) can be connected via an internal OR
gate to the IRQ interrupt function by a mask option. All the port A pins
can have software programmable pulldown devices provided by another
mask option. See Section 7. Parallel Input/Output (I/O) for more
details on the I/O ports.
1.7.6 PB0
The state of the PB0 pin is software programmable and is configured as
an input during power-on or reset, except in serial program mode. This
pin can have a software programmable pulldown device provided by a
mask option. See Section 7. Parallel Input/Output (I/O) for more
details on the I/O ports.
1.7.7 PB1/OSC3
The state of the PB1/OSC3 pin is software programmable and is
configured as an input during power-on or reset, except in serial program
mode or when the 3-pin RC oscillator configuration is selected by mask
option. This pin can have a software programmable pulldown device
provided by a mask option. See Section 7. Parallel Input/Output (I/O)
for more details on the I/O ports.
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Freescale Semiconductor, Inc.
For More Information On This Product,
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ARCHIVED
BY
FREESCALE
SEMICONDUCT
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2006
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