參數(shù)資料
型號(hào)： MC68HC05JB3DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 141/148頁
文件大?。?/td> 1600K
代理商： MC68HC05JB3DW
GENERAL RELEASE SPECIFICATION
November 5, 1998
MOTOROLA
UNIVERSAL SERIAL BUS MODULE
MC68HC05JB3
10-24
REV 1
TX1E — Endpoint 1/Endpoint 2 Transmit Enable
This read/write bit enables a transmit to occur when the USB Host controller
sends an IN token to Endpoint 1 or Endpoint 2. The appropriate endpoint
enable bit, ENABLE1 or ENABLE2 bit in the UCR2 register, should also be set.
Software should set the TX1E bit when data is ready to be transmitted. It must
be cleared by software when no more data needs to be transmitted.
If this bit is 0 or the TXD1F is set, the USB will respond with a NAK handshake
to any Endpoint 1 or Endpoint 2 directed IN tokens. Reset clears this bit.
1 =
Data is ready to be sent.
0 =
Data is not ready. Respond with NAK.
FRESUM — Force Resume
This read/write bit forces a resume state (“K” or non-idle state) onto the USB
data lines to initiate a remote wake-up. Software should control the timing of the
forced resume to be between 10ms and 15 ms. Setting this bit will not cause
the RESUMF bit to set.
1 =
Force data lines to “K” state.
0 =
Default.
TP1SIZ3-TP1SIZ0 — Endpoint 1/Endpoint 2 Transmit Data Packet Size
These read/write bits store the number of transmit data bytes for the next IN
token request for Endpoint 1 or Endpoint 2. These bits are cleared by reset.
10.5.6 USB Control Register 2 (UCR2)
TX1STR — Clear Transmit First Flag
Writing a logic 1 to this write-only bit will clear the TX1ST bit if it is set. Writing a
logic 0 to the TX1STR has no effect. Reset clears this bit.
TX1ST — Transmit First Flag
This read-only bit is set if the Endpoint 0 Data Transmit Flag (TXD0F) is set
when the USB control logic is setting the Endpoint 0 Data Receive Flag
(RXD0F). That is, this bit will be set if an Endpoint 0 Transmit Flag is still set at
the end of an Endpoint 0 reception. This bit lets the rmware know that the
Endpoint 0 transmission happened before the Endpoint 0 reception. Reset
clears this bit.
1 =
IN transaction occurred before SETUP/OUT.
0 =
IN transaction occurred after SETUP/OUT.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UCR2
R
0
TX1ST
0
ENABLE2 ENABLE1
STALL2
STALL1
$0037
W
TX1STR
reset
:
-
0
-
0000
= Unimplemented
Figure 10-25. USB Control Register 2 (UCR2)
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