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參數(shù)資料
| 型號(hào)： | MC68HC05J5AP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁(yè)數(shù)： | 11/106頁(yè) |
| 文件大小： | 1419K |
| 代理商： | MC68HC05J5AP |
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GENERAL RELEASE SPECIFICATION
July 16, 1999
GENERAL DESCRIPTION
MC68HC05J5A
1-2
REV 2.1
14 Bidirectional I/O pins (10 I/O pins on 16-pin package)
– PA0-PA5, PB0, and PB3-PB5: with software programmable input pull-
down devices
– PB1, PB2, PA6 and PA7: open-drained I/O pins with software
programmable pull-up devices
– PA6, PA7, and PB1: with slow output falling transition feature
– PA7: with falling-edge interrupt capability
– PA0-PA3: with maskable rising-edge only or rising-edge and high
level interrupt capability
– 20-pin package: PB1 and PB2, each with 25mA current sink
capability
– 16-pin package: PB1 with 50mA current sink capability
Computer Operation Properly (COP) Watchdog
Low Voltage Reset Circuit
Illegal Address Reset
20-pin PDIP, 20-pin SOIC, 16-pin PDIP, and 16-pin SOIC packages
1.2
MASK OPTIONS
The following mask options are available on the MC68HC05J5A:
1.3
MCU STRUCTURE
Figure 1-1 shows the structure of MC68HC05J5A MCU.
MASK
OPTION
STOP instruction convert to WAIT
[Enabled] or [Disabled]
External interrupt pins (IRQ, PA0-PA3)
[Edge-triggered] or [Edge and level triggered]
Port A and Port B pull-down/pull-up resistors
[Enabled] or [Disabled]
PA0-PA3 external interrupt capability
[Enabled] or [Disabled]
Oscillator Delay Option (internal clock cycles)
[224] or [4064]
Low Voltage Reset
[Enabled] or [Disabled]
COP Watchdog Timer
[Enabled] or [Disabled]
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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