參數(shù)資料
型號(hào)： MC68HC05J5AJDWR2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO16
封裝： SOIC-16
文件頁數(shù)： 82/106頁
文件大小： 1069K
代理商： MC68HC05J5AJDWR2
July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
INSTRUCTION SET
MOTOROLA
REV 2.1
10-9
BHCC
rel
Branch if Half-Carry
Bit Clear
PC
← (PC) + 2 + rel ? H = 0
—————
REL
28
rr
3
BHCS
rel
Branch if Half-Carry
Bit Set
PC
← (PC) + 2 + rel ? H = 1
—————
REL
29
rr
3
BHI
rel
Branch if Higher
PC
← (PC) + 2 + rel ? C ∨ Z = 0 —————
REL
22
rr
3
BHS
rel
Branch if Higher or
Same
PC
← (PC) + 2 + rel ? C = 0
—————
REL
24
rr
3
BIH
rel
Branch if IRQ Pin
High
PC
← (PC) + 2 + rel ? IRQ = 1 —————
REL
2F
rr
3
BIL
rel
Branch if IRQ Pin
Low
PC
← (PC) + 2 + rel ? IRQ = 0 —————
REL
2E
rr
3
BIT #
opr
BIT
opr
BIT
opr
BIT
opr,X
BIT
opr,X
BIT ,X
Bit Test
Accumulator with
Memory Byte
(A)
∧ (M)
— — ¤¤ —
IMM
DIR
EXT
IX2
IX1
IX
A5
B5
C5
D5
E5
F5
ii
dd
hh ll
ee ff
ff
p
2
3
4
5
4
3
BLO
rel
Branch if Lower
(Same as BCS)
PC
← (PC) + 2 + rel ? C = 1
—————
REL
25
rr
3
BLS
rel
Branch if Lower or
Same
PC
← (PC) + 2 + rel ? C ∨ Z = 1 —————
REL
23
rr
3
BMC
rel
Branch if Interrupt
Mask Clear
PC
← (PC) + 2 + rel ? I = 0
—————
REL
2C
rr
3
BMI
rel
Branch if Minus
PC
← (PC) + 2 + rel ? N = 1
—————
REL
2B
rr
3
BMS
rel
Branch if Interrupt
Mask Set
PC
← (PC) + 2 + rel ? I = 1
—————
REL
2D
rr
3
BNE
rel
Branch if Not Equal
PC
← (PC) + 2 + rel ? Z = 0
—————
REL
26
rr
3
BPL
rel
Branch if Plus
PC
← (PC) + 2 + rel ? N = 0
—————
REL
2A
rr
3
BRA
rel
Branch Always
PC
← (PC) + 2 + rel ? 1 = 1
—————
REL
20
rr
3
BRCLR
n opr rel Branch if bit n clear
PC
← (PC) + 2 + rel ? Mn = 0
———— ¤
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
5
BRSET
n opr rel Branch if Bit n Set
PC
← (PC) + 2 + rel ? Mn = 1
———— ¤
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
5
BRN
rel
Branch Never
PC
← (PC) + 2 + rel ? 1 = 0
—————
REL
21
rr
3
Table 10-6. Instruction Set Summary (Continued)
Source
Form
Operation
Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
H I NZC
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