參數(shù)資料
型號(hào)： MC68HC05J5ADWR2
廠(chǎng)商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20
封裝： SOIC-20
文件頁(yè)數(shù)： 64/106頁(yè)
文件大?。?/td> 1069K
代理商： MC68HC05J5ADWR2
GENERAL RELEASE SPECIFICATION
July 16, 1999
MOTOROLA
16-BIT TIMER
MC68HC05J5A
9-2
REV 2.1
The basis of the 16-bit Timer is a 16-bit free-running counter which increases in
count with each internal bus clock cycle. The counter is the timing reference for
the input capture and output compare functions. The input capture and output
compare functions provide a means to latch the times at which external events
occur, to measure input waveforms, and to generate output waveforms and timing
delays. Software can read the value in the 16-bit free-running counter at any time
without affect the counter sequence.
Because of the 16-bit timer architecture, the I/O registers are pairs of 8-bit regis-
ters. Each register pair contains the high and low byte of that function. Generally,
accessing the low byte of a specic timer function allows full control of that func-
tion; however, an access of the high byte inhibits that specic timer function until
the low byte is also accessed.
Because the counter is 16 bits long and preceded by a xed divide-by-four pres-
caler, the counter rolls over every 262,144 internal clock cycles. Timer resolution
with a 4MHz crystal oscillator is 2 microsecond/count.
The interrupt capability and the input capture edge are controlled by the timer con-
trol register (T1CR) located at $0012 and the status of the interrupt ags can be
read from the timer status register (T1SR) located at $0013.
9.1
TIMER1 COUNTER REGISTERS (TCNTH, TCNTL)
The functional block diagram of the 16-bit free-running timer counter and timer
registers is shown in Figure 9-2. The timer registers include a transparent buffer
latch on the LSB of the 16-bit timer counter.
Figure 9-2. 16-Bit Timer Counter Block Diagram
T1OIE
TCNTH ($18)
TCNTL LSB
16-BIT COUNTER
÷ 4
INTERNAL
(fOSC ÷ 2)
TIMER1 CONTROL REG.
TIMER1
REQUEST
OVERFLOW (T1OF)
RESET
CLOCK
INTERRUPT
TCNTL ($19)
T1OF
TIMER1 STATUS REG.
$12
$13
INTERNAL
($FFFC)
DATA
READ
TCNTH
READ
TCNTL
READ
LATCH
BUS
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