參數(shù)資料
型號(hào): MC68HC05J3CDW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20
封裝: PLASTIC, SOIC-20
文件頁(yè)數(shù): 76/92頁(yè)
文件大?。?/td> 912K
代理商: MC68HC05J3CDW
MOTOROLA
9-6
MC68HC05J3
ELECTRICAL SPECIFICATIONS
9
(1) Since the 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting factor in
determining the timer resolution.
(2) The minimum period tTLTL should not be less than the number of cycles it takes to execute the capture
interrupt service routine plus 24 tCYC.
(3) The minimum period tILIL should not be less than the number of cycles it takes to execute the interrupt
service routine plus 21 tCYC.
Table 9-6 AC electrical characteristics for 3.3V operation
(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH
Characteristic
Symbol
Min
Max
Unit
Frequency of operation
Crystal
External clock
fOSC
dc
2.1
MHz
Internal operating frequency
Crystal (fOSC /2)
External clock (fOSC /2)
fOP
dc
1.05
MHz
Processor cycle time
tCYC
1000
ns
Ceramic resonator start-up time
tOXOV
20
ms
Ceramic resonator STOP recovery start-up time
tILCH
20
ms
OSC1 pulse width
tOH, tOL
200
ns
RESET pulse width
tRL
1.5
tCYC
16-bit timer
Resolution(1)
Input capture pulse width
Input capture pulse period
tRESL
tTLTH
tTLTL
500
(2)
4
tCYC
ns
tCYC
Power-on reset delay
tPORL
4064
tCYC
Interrupt pulse width low (edge-triggered)
tILIH
250
ns
Interrupt pulse period (see Figure 9-2)
tILIL
(3)
tCYC
Figure 9-2 External interrupt timing
IRQ
tILIH
tILIL
Edge-sensitive trigger — The minimum tILIH is either 125ns (VDD=5V) or 250ns (VDD=3.3V). The minimum period
tILIL should not be less than the number of cycles it takes to execute the interrupt service routine plus 21 tCYC.
Edge and level sensitive trigger — If IRQ remains low after the initial interrupt is serviced, the MCU recognises the
interrupt until the IRQ line returns to a high level.
TPG
75
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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