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參數(shù)資料
| 型號(hào)： | MC68HC05E6CDW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁(yè)數(shù)： | 95/140頁(yè) |
| 文件大?。?/td> | 1584K |
| 代理商： | MC68HC05E6CDW |
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Programmable Timer
MC68HC05E6 — Rev. 1.0
Programmable Timer
Input capture high
register, Input
capture low
register
The two 8-bit registers that make up the 16-bit input capture register are
read-only, and are used to latch the value of the free-running counter after
the input capture edge detector senses a valid transition. The level
transition that triggers the counter transfer is defined by the input edge bit
(IEDG). The most significant 8 bits are stored in the input capture high
register at $14, the least significant in the input capture low register at $15.
The result obtained from an input capture will be one greater than the
value of the free-running counter on the rising edge of the internal bus
clock preceding the external transition. This delay is required for internal
synchronisation. Resolution is one count of the free-running counter,
which is four internal bus clock cycles. The free-running counter
contents are transferred to the input capture register on each valid signal
transition whether the input capture flag (ICF) is set or clear. The input
capture register always contains the free-running counter value that
corresponds to the most recent input capture. After a read of the input
capture register MSB ($14), the counter transfer is inhibited until the LSB
($15) is also read. This characteristic causes the time used in the input
capture software routine and its interaction with the main program to
determine the minimum pulse period. A read of the input capture register
LSB ($15) does not inhibit the free-running counter transfer since the two
actions occur on opposite edges of the internal bus clock.
The contents of the input capture register are undefined following reset.
Output compare
function
‘Output compare’ is a technique that may be used, for example, to
generate an output waveform, or to signal when a specific time period
has elapsed, by presetting the output compare register to the
appropriate value.
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Input capture high (ICH)
$0014 (bit 15)
(bit 8) Undened
Input capture low (ICL)
$0015
Undened
8-ptimer
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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| MC68HC05E6MFB | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| MC68HC05E6VDWR2 | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC705E6MFB | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| MC68HC705E6CFB | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| MC68HC705E6VDWR2 | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05E6CFB | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC05E6DW | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC05E6FB | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC05E6MDW | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC05E6MFB | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
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