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參數(shù)資料
| 型號： | MC68HC05E1DWR3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 62/86頁 |
| 文件大小： | 491K |
| 代理商： | MC68HC05E1DWR3 |
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Timer, Phase-Locked Loop, and Custom Periodic Interrupt
Phase-Locked Loop Synthesizer
MC68HC05E1 — Revision 2.0
General Release Specication
MOTOROLA
Timer, Phase-Locked Loop, and Custom Periodic Interrupt
65
To change PLL frequencies, follow the procedure outlined below:
1. Clear BCS to enable the low frequency bus rate,
2. Clear PLLON to disable the PLL and select manual high
bandwidth,
3. Select the speed using PS1 and PS0,
4. Set PLLON to enable the PLL,
5. Wait a time of 90% tPLLS for the PLL frequency to stabilize and
select manual low bandwidth, wait another 10% tPLLS,
6. Set BCS to switch to the high frequency bus rate.
The user should not switch among the high speeds with the BCS bit set.
Following the procedure above will prevent possible bursts of high
frequency operation during the re-configuration of the PLL.
The PLL loop filter has two bandwidths which are automatically selected
by the PLL if AUTO=1. Whenever the PLL is first enabled, the wide
bandwidth mode is used. This enables the PLL frequency to ramp up
quickly. When the output frequency is near the desired frequency, the
filter is switched to the narrow bandwidth mode to make the final
frequency more stable. The use of automatic bandwidth is not
recommended at this time. Manual bandwidth control can be done by
clearing AUTO in the PLLCR and setting the appropriate value for BWC.
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