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參數資料
| 型號： | MC68HC05E1DW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數： | 61/86頁 |
| 文件大?。?/td> | 709K |
| 代理商： | MC68HC05E1DW |
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General Release Specication
MC68HC05E1 — Revision 2.0
64
Timer, Phase-Locked Loop, and Custom Periodic Interrupt
MOTOROLA
Timer, Phase-Locked Loop, and Custom Periodic
6.4 Phase-Locked Loop Synthesizer
The phase-locked loop (PLL) consists of a variable bandwidth loop filter,
a voltage controlled oscillator (VCO), a feedback frequency divider, and
a digital phase detector. The PLL requires an external loop filter
capacitor (typically 0.1 uf) connected between XFC and VDDSYN. This
capacitor should be located as close to the chip as possible to minimize
noise. VDDSYN is the supply source for the PLL and should be bypassed
to minimize noise. The VDDSYN bypass cap should be as close as
possible to the chip.
Figure 6-4. PLL Circuit
The phase detector compares the frequency and phase of the feedback
frequency (tFB) and the crystal oscillator reference frequency (tREF) and
generates the output, PCOMP, as shown in Figure 6-4. The output
wave-form is then integrated and amplified. The resultant dc voltage is
applied to the voltage controlled oscillator. The output of the VCO is
divided by a variable frequency divider of 256, 128, 64, or 32 to provide
the feedback frequency for the phase detector.
loop filter
VCO
Phase
PCOMP
PLLOUT
Frequency
Divider
t
FB
OSC1
XFC
Crystal
Oscillator
PS1
PS0
To clock
V
DDSYN
Detect
generation
circuitry
Clock
Select
BCS
t
REF
and
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F
0.1
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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