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參數(shù)資料
| 型號(hào)： | MC68HC05CT4FN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.048 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 116/142頁 |
| 文件大?。?/td> | 3470K |
| 代理商： | MC68HC05CT4FN |
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Synchronous Serial Interface (SSI)
SSI Registers
MC68HC05CT4 — Rev. 2.0
General Release Specification
Synchronous Serial Interface (SSI)
NON-DISCLOSURE
AGREEMENT
REQUIRED
9.4.2 SSI Status Register
This register is located at address $001C and contains two bits. Reset
clears both of these bits.
SF — SSI Flag
This bit is set upon occurrence of the last rising clock edge and
indicates that a data transfer has taken place. If MSTR = 0 and
SIE = 0, this bit has no effect on any further transmissions and can be
ignored without problem. However, the SF flag must be clear to write
the data register, or if SIE = 1 to clear the interrupt. If MSTR = 1, the
SF flag must be cleared between transfers. The SF flag can be
cleared three different ways: (1) by reading the SSR with SF set,
followed by a read or write of the serial data register, (2) by a system
reset, or, (3) by disabling the SSI. If the SF flag is cleared before the
last edge of the next byte, it will be set again.
DCOL — Data Collision
This is a read-only status bit, which indicates that an invalid access to
the data register was made. An invalid access can be one of the
following conditions:
An access of the SDR register in the middle of a transfer (after the
first falling edge of SCK and before SF is set)
An access of the SDR register made before an access of the SSR
register (after SF is set)
DCOL is cleared by reading the status register with SF set followed
by a read or write of the data register. A reset also clears this bit.
Address:
$001C
Bit 7
654321
Bit 0
Read:
SF
DCOL
000000
Write:
Reset:
00000000
Figure 9-4. SSI Status Register (SSR)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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