參數(shù)資料
型號: MC68HC05C9ECP
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝: PLASTIC, DIP-40
文件頁數(shù): 129/144頁
文件大小: 1628K
代理商: MC68HC05C9ECP
Serial Communications Interface (SCI)
SCI I/O Registers
MC68HC05C9E
Advance Information
MOTOROLA
Serial Communications Interface (SCI)
85
N
O
N-D
I
SC
L
O
SU
R
E
AG
R
EEMENT
R
E
Q
U
IR
ED
9.12.4 SCI Status Register
The SCI status register (SCSR), shown in Figure 9-11, contains flags to
signal these conditions:
Transfer of SCDR data to transmit shift register complete
Transmission complete
Transfer of receive shift register data SCDR complete
Receiver input idle
Noisy data
Framing error
TDRE — Transmit Data Register Empty Flag
This clearable, read-only flag is set when the data in the SCDR
transfers to the transmit shift register. TDRE generates an interrupt
request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by
reading the SCSR with TDRE set and then writing to the SCDR. Reset
sets the TDRE bit. Software must initialize the TDRE bit to logic 0 to
avoid an instant interrupt request when turning the transmitter on.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
TC — Transmission Complete Flag
This clearable, read-only flag is set when the TDRE bit is set, and no
data, preamble, or break character is being transmitted. TDRE
generates an interrupt request if the TCIE bit in SCCR2 is also set.
Clear the TC bit by reading the SCSR with TC set, and then writing to
Address:
$0010
Bit 7
6543
2
1
Bit 0
Read:
TDRE
TC
RDRF
IDLE
OR
NF
FE
Write:
Reset:
11000
0
= Unimplemented
Figure 9-11. SCI Status Register (SCSR)
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