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| 型號(hào)： | MC68HC05C9AMP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁(yè)數(shù)： | 89/124頁(yè) |
| 文件大小： | 774K |
| 代理商： | MC68HC05C9AMP |
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Functional Description
MC68HC05C9A Advance Information Data Sheet, Rev. 5.1
Freescale Semiconductor
67
characters. In cases where there is only one SPI slave MCU, its SS line could be tied to VSS as long as
CPHA = 1 clock modes are used.
10.4 Functional Description
Figure 10-2 shows a block diagram of the serial peripheral interface circuitry. When a master device
transmits data to a slave via the MOSI line, the slave device responds by sending data to the master
device via the master’s MISO line. This implies full duplex transmission with both data out and data in
synchronized with the same clock signal. Thus, the byte transmitted is replaced by the byte received and
eliminates the need for separate transmit-empty and receive-full status bits. A single status bit (SPIF) is
used to signify that the input/output (I/O) operation has been completed.
The SPI is double buffered on read, but not on write. If a write is performed during data transfer, the
transfer occurs uninterrupted, and the write will be unsuccessful. This condition will cause the write
collision (WCOL) status bit in the SPSR to be set. After a data byte is shifted, the SPIF flag of the SPSR
is set.
In the master mode, the SCK pin is an output. It idles high or low, depending on the CPOL bit in the SPCR,
until data is written to the shift register, at which point eight clocks are generated to shift the eight bits of
data and then SCK goes idle again.
Figure 10-2. Serial Peripheral Interface Block Diagram
S
6
7
543210
SPE
SPIE
SPI CONTROL REGISTER (SPCR)
MSTR
CPOL
CPHA
SPR1
SPR2
$000A
WCOL
SPIF
SPI STATUS REGISTER (SPSR)
0
MODF
0
$000B
BIT 6
BIT 7
SPI DATA REGISTER (SPDR)
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
$000C
DWOM
00
SPI SHIFT REGISTER
DIVIDER
CLOCK
LOGIC
SPDR ($000C)
7 6 5 4 3 2 1 0
MODF
WCOL
SPIF
SPR1
SPR0
CPOL
CPHA
MSTR
SPE
SPIE
PD3/
MOSI
PD2/
MISO
÷ 2
÷ 32
÷ 16
÷ 4
SELECT
SPI
CONTROL
INTERNAL DATA BUS
MSTR
S
M
INTERNAL
CLOCK
(XTAL
÷2)
SPI CLOCK (MASTER)
SPI INTERRUPT REQUEST
SHIFT
CLOCK
PD4/
SCK
PD5/
SS
SLAVE
SPI
MASTER
CLOCK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05C9AP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC68HC05C9CP | 制造商:Motorola Inc 功能描述:IC UP HCMOS 68HC05C9CP DIP40 0 |
| MC68HC05C9E | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC68HC05C9ECFB | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC68HC05C9ECP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
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