- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69026 > MC68HC05C9AMFN (FREESCALE SEMICONDUCTOR INC) 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44 PDF資料下載
參數(shù)資料
| 型號： | MC68HC05C9AMFN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 89/124頁 |
| 文件大?。?/td> | 774K |
| 代理商： | MC68HC05C9AMFN |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁當前第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁
Functional Description
MC68HC05C9A Advance Information Data Sheet, Rev. 5.1
Freescale Semiconductor
67
characters. In cases where there is only one SPI slave MCU, its SS line could be tied to VSS as long as
CPHA = 1 clock modes are used.
10.4 Functional Description
Figure 10-2 shows a block diagram of the serial peripheral interface circuitry. When a master device
transmits data to a slave via the MOSI line, the slave device responds by sending data to the master
device via the master’s MISO line. This implies full duplex transmission with both data out and data in
synchronized with the same clock signal. Thus, the byte transmitted is replaced by the byte received and
eliminates the need for separate transmit-empty and receive-full status bits. A single status bit (SPIF) is
used to signify that the input/output (I/O) operation has been completed.
The SPI is double buffered on read, but not on write. If a write is performed during data transfer, the
transfer occurs uninterrupted, and the write will be unsuccessful. This condition will cause the write
collision (WCOL) status bit in the SPSR to be set. After a data byte is shifted, the SPIF flag of the SPSR
is set.
In the master mode, the SCK pin is an output. It idles high or low, depending on the CPOL bit in the SPCR,
until data is written to the shift register, at which point eight clocks are generated to shift the eight bits of
data and then SCK goes idle again.
Figure 10-2. Serial Peripheral Interface Block Diagram
S
6
7
543210
SPE
SPIE
SPI CONTROL REGISTER (SPCR)
MSTR
CPOL
CPHA
SPR1
SPR2
$000A
WCOL
SPIF
SPI STATUS REGISTER (SPSR)
0
MODF
0
$000B
BIT 6
BIT 7
SPI DATA REGISTER (SPDR)
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
$000C
DWOM
00
SPI SHIFT REGISTER
DIVIDER
CLOCK
LOGIC
SPDR ($000C)
7 6 5 4 3 2 1 0
MODF
WCOL
SPIF
SPR1
SPR0
CPOL
CPHA
MSTR
SPE
SPIE
PD3/
MOSI
PD2/
MISO
÷ 2
÷ 32
÷ 16
÷ 4
SELECT
SPI
CONTROL
INTERNAL DATA BUS
MSTR
S
M
INTERNAL
CLOCK
(XTAL
÷2)
SPI CLOCK (MASTER)
SPI INTERRUPT REQUEST
SHIFT
CLOCK
PD4/
SCK
PD5/
SS
SLAVE
SPI
MASTER
CLOCK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC05C9AMP | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| MC68HC05C9ECP | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| MC68HC05CC2B | 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PDIP42 |
| MC68HC05CJ4FB | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| MC68HC705CJ4FB | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05C9AMP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC68HC05C9AP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC68HC05C9CP | 制造商:Motorola Inc 功能描述:IC UP HCMOS 68HC05C9CP DIP40 0 |
| MC68HC05C9E | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC68HC05C9ECFB | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
發(fā)布緊急采購，3分鐘左右您將得到回復。