參數(shù)資料
型號: MC68HC05C9AMB
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP42
封裝: PLASTIC, SDIP-42
文件頁數(shù): 102/162頁
文件大?。?/td> 1093K
代理商: MC68HC05C9AMB
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Interrupts
Advance Information
MC68HC05C9A Rev. 5.0
44
Interrupts
MOTOROLA
4.5 Timer Interrupt
Three different timer interrupt flags cause a timer interrupt whenever
they are set and enabled. The interrupt flags are in the timer status
register (TSR), and the enable bits are in the timer control register
(TCR). Any of these interrupts will vector to the same interrupt service
routine, located at the address specified by the contents of memory
locations $3FF8 and $3FF9.
4.6 SCI Interrupt
Five different SCI interrupt flags cause an SCI interrupt whenever they
are set and enabled. The interrupt flags are in the SCI status register
(SCSR), and the enable bits are in the SCI control register 2 (SCCR2).
Any of these interrupts will vector to the same interrupt service routine,
located at the address specified by the contents of memory locations
$3FF6 and $3FF7.
4.7 SPI Interrupt
Two different SPI interrupt flags cause an SPI interrupt whenever they
are set and enabled. The interrupt flags are in the SPI status register
(SPSR), and the enable bits are in the SPI control register (SPCR).
Either of these interrupts will vector to the same interrupt service routine,
located at the address specified by the contents of memory locations
$3FF4 and $3FF5.
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