參數(shù)資料
型號: MC68HC05C9AFN
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 137/160頁
文件大?。?/td> 4128K
代理商: MC68HC05C9AFN
NON-DISCLOSURE
AGREEMENT
REQUIRED
Serial Communications Interface (SCI)
General Release Specification
MC68HC05C9A Rev. 4.0
Serial Communications Interface (SCI)
9.12 Start Bit Detection
When the input (idle) line is detected low, it is tested for three more
sample times (referred to as the start edge verification samples in
Figure 9-4). If at least two of these three verification samples detect a
logic zero, a valid start bit has been detected; otherwise, the line is
assumed to be idle. A noise flag is set if all three verification samples do
not detect a logic zero. Thus, a valid start bit could be assumed with a
set noise flag present.
If a framing error has occurred without detection of a break (10 zeros for
8-bit format or 11 zeros for 9-bit format), the circuit continues to operate
as if there actually was a stop bit, and the start edge will be placed
artificially. The last bit received in the data shift register is inverted to a
logic one, and the three logic one start qualifiers (shown in Figure 9-4)
are forced into the sample shift register during the interval when
detection of a start bit is anticipated (see Figure 9-6); therefore, the start
bit will be accepted no sooner than it is anticipated.
If the receiver detects that a break (RDRF = 1, FE = 1, receiver data
register = $003B) produced the framing error, the start bit will not be
artificially induced and the receiver must actually detect a logic one
before the start bit can be recognized (see Figure 9-7).
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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