參數(shù)資料
型號(hào): MC68HC05C9A
廠商: Motorola, Inc.
元件分類: 8位微控制器
英文描述: 8-Bit Microcontroller(8位微控制器)
中文描述: 8位微控制器(8位微控制器)
文件頁數(shù): 50/160頁
文件大?。?/td> 783K
代理商: MC68HC05C9A
L
G
R
Resets
General Release Specification
MC68HC05C9A
Rev. 4.0
50
Resets
MOTOROLA
5.6 COP During Wait Mode
The COP will continue to operate normally during wait mode. The
software must pull the device out of wait mode periodically and reset the
COP to prevent a system reset.
5.7 COP During Stop Mode
Stop mode disables the oscillator circuit and thereby turns the clock off
for the entire device. The COP counter will be reset when stop mode is
entered. If a reset is used to exit stop mode, the COP counter will be
reset after the 4064 cycles of delay after stop mode. If an IRQ is used to
exit stop mode, the COP counter will not be reset after the 4064-cycle
delay and will have that many cycles already counted when control is
returned to the program.
In the event that an inadvertent STOP instruction is executed, the COP
will not provide a reset. The clock monitor function provides protection
for this situation.
5.8 Clock Monitor Reset
The clock monitor circuit can provide a system reset if the clock stops for
any reason, including stop mode. When the CME bit in the COP control
register is set, the clock monitor detects the absence of the internal bus
clock for a certain period of time. The timeout period is dependent on the
processing parameters and varies from 5
μ
s to 100
μ
s, which implies
that systems using a bus clock rate of 200 kHz or less should not use the
clock monitor.
If a slow or absent clock is detected, the clock monitor causes a system
reset. The reset is issued to the external system via the bidirectional
RESET pin for four bus cycles if the clock is slow or until the clocks
recover in the case where the clocks are absent.
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