
Freescale
11-2
MC68HC05B6
Rev. 4.1
ELECTRICAL SPECIFICATIONS
11
11.2
DC electrical characteristics
Table 11-2 DC electrical characteristics for 5V operation
(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)
Characteristic(1)
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient
switching currents inherent in CMOS designs (see Section 2).
Symbol
Min
Typ(2)
(2) Typical values are at mid point of voltage range and at 25°C only.
Max
Unit
Output voltage
ILOAD = – 10 A
ILOAD = +10 A
VOH
VOL
VDD – 0.1
—
0.1
V
Output high voltage (ILOAD = 0.8mA)
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2
Output high voltage (ILOAD = 1.6mA)
TDO, SCLK, PLMA, PLMB
VOH
VDD – 0.8
VDD – 0.4
—
V
Output low voltage (ILOAD = 1.6mA)
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,
TDO, SCLK, PLMA, PLMB
Output low voltage (ILOAD = 1.6mA)
RESET
VOL
—0.1
0.4
1
V
Input high voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1,
IRQ, RESET, TCAP1, TCAP2, RDI
VIH
0.7VDD
—VDD
V
Input low voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ,
RESET,TCAP1, TCAP2, RDI
VIL
VSS
—0.2VDD
V
Supply current(3)
STOP
0 to 70 (standard)
– 40 to 85 (extended)
– 40 to 105 (extended)
– 40 to 125 (automotive)
(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 4.2MHz); all inputs 0.2 V from
rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2).
STOP /WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH =VDD – 0.2 V: STOP IDD measured with
OSC1 = VDD.
WAIT IDD is affected linearly by the OSC2 capacitance.
IDD
—
3.5
0.5
1
0.35
2
—
6
1.5
2
1
10
20
60
mA
A
High-Z leakage current
PA0–7, PB0–7, PC0–7, TDO, RESET, SCLK
IIL
—
±0.2
±1
A
Input current (0 to 70)
IRQ, OSC1, TCAP1, TCAP2, RDI,
PD0/AN0-PD7/AN7 (channel not selected)
IIN
—
±0.2
±1
mA
Input current (– 40 to 125)
IRQ, OSC1, TCAP1, TCAP2, RDI,
IIN
——
±5
A
Capacitance
Ports (as input or output), RESET, TDO, SCLK
IRQ, TCAP1, TCAP2, OSC1, RDI
PD0/AN0–PD7/AN7 (A/D off)
PD0/AN0–PD7/AN7 (A/D on)
COUT
CIN
—
12
22
12
8
—
pF
134
135
136
137
138